Semiconductor Adhesion Layer Load Balancing via Partial Etching
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Solution Overview
Problem
In semiconductor device manufacturing, unbalanced load during chemical mechanical planarization due to the absence of a bonding pad leads to uneven wafer surfaces and device failure, necessitating a solution to balance the load and reduce manufacturing costs.
Innovation Solution
A method involving the formation of a mask pattern with sub-resolution auxiliary and exposable patterns for photolithography, followed by anisotropic etching to create openings and via holes in the adhesion layer, which are filled with conductive material to balance the load during planarization, using a dielectric cover layer and adhesion layers with lead-out and non-lead-out regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bonding pad is formed on the wafer for electrical lead-out, then electrical connection is achieved, but the load during chemical mechanical planarization becomes unbalanced causing uneven wafer surface
Solution Approach 1:
The adhesion layer is divided into two regions with different properties: a lead-out region that is etched away to form openings for electrical connection, and a non-lead-out region that retains the adhesion layer to maintain load balance during planarization. This local differentiation allows simultaneous achievement of electrical connectivity and surface uniformity.
Solution Approach 2:
The adhesion layer is segmented into functionally distinct regions (lead-out and non-lead-out areas) through selective etching. The mask pattern is also segmented with exposable regions corresponding to lead-out areas and sub-resolution auxiliary patterns corresponding to non-lead-out areas, enabling differential processing to resolve the contradiction.
2Ease of manufacture
If the adhesion layer is completely removed in the lead-out region, then electrical lead-out is achieved, but the load balance during planarization deteriorates
Solution Approach 1:
The adhesion layer removal is applied locally only to the lead-out region where electrical connection is needed, while the non-lead-out region retains the adhesion layer. This localized approach achieves electrical lead-out functionality without compromising overall load balance during planarization.
Solution Approach 2:
The processing is segmented into different zones: the lead-out region undergoes complete adhesion layer removal for electrical access, while the non-lead-out region maintains the adhesion layer for load balancing, achieving both goals simultaneously through spatial segmentation.
3Manufacturing precision
If sub-resolution auxiliary patterns are added to the mask, then the manufacturing process complexity increases, but the load balance during planarization is improved
Solution Approach 1:
Multiple functions are merged into a single mask pattern: the exposable patterns define the lead-out regions, while the sub-resolution auxiliary patterns define the non-lead-out regions. Both patterns are processed in one photolithography step, combining what could have been separate processing steps into one operation, reducing overall process complexity despite the mask's increased detail.
Solution Approach 2:
The mask pattern serves multiple functions simultaneously: it defines both the lead-out regions (through exposable patterns) and the non-lead-out regions (through sub-resolution auxiliary patterns) in a single layer, making the mask a multi-functional element that controls differential etching across the wafer surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves load balance during planarization, reduces manufacturing costs, and prevents device failure by ensuring a uniform wafer surface through the strategic formation of openings and via holes in the semiconductor device.
Implementation Method 1
transferring a pattern of a mask to the photoresist layer through photolithography
Implementation Method 2
performing anisotropic etching on the adhesion layer by using the photoresist layer
Data Source
AI summary
A semiconductor device and a method for manufacturing the same. When a pattern for etching is formed through photolithography after forming a photoresist layer on an adhesion layer, a sub-resolution auxiliary pattern of the mask is above the non-lead-out region, and an exposable pattern of the mask is above a lead-out region. In the photolithography, a first partial exposure region exposed partially in depth is formed in the photoresist layer corresponding to the sub-resolution auxiliary pattern, and an exposed pattern that is exposed completely is formed in the photoresist layer corresponding to the exposable pattern. After anisotropic etching on the adhesion layer through the photoresist layer, both an opening running through a partial thickness of the adhesion layer and a via hole running through the adhesion layer are formed. The opening balances a load in planarization during a process of filling the via hole.