Adhesion Promoter Layer for Barrierless Semiconductor Vias
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing advanced integrated circuits due to increased complexity and the need for improved processes to maintain efficiency and cost-effectiveness as geometry sizes decrease and functional density increases, requiring innovative methods for forming semiconductor devices.
Innovation Solution
The method involves forming semiconductor devices using a substrate with patterned fins, gate stacks, source/drain regions, and dielectric layers, along with the selective deposition of an adhesion promoter layer and the formation of barrierless vias and contacts to enhance adhesion and reduce resistivity, utilizing techniques like CVD, ALD, and photolithography processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional manufacturing processes are used for scaling down geometry sizes, then production efficiency and cost-effectiveness are improved, but manufacturing complexity increases and adhesion problems occur
Solution Approach 1:
An adhesion promoter layer is deposited on the dielectric layer before forming the conductive layer. This preliminary action ensures that adhesion requirements are met in advance, preventing subsequent manufacturing issues and reducing the need for complex corrective processes, thereby managing manufacturing complexity while maintaining productivity
2Reliability
If conventional via formation methods are used, then manufacturing process is simpler, but adhesion between conductive layer and dielectric layer is insufficient
Solution Approach 1:
An adhesion promoter layer is introduced as an intermediary between the dielectric layer and the conductive layer. This intermediate layer specifically addresses the adhesion problem without requiring fundamental changes to the overall manufacturing process, thereby improving reliability while limiting increases in process complexity
3Reliability
If barrier layers are used in via formation, then adhesion is improved, but resistivity increases
Solution Approach 1:
The material composition of the adhesion promoter layer is specifically selected and tuned to provide adequate adhesion while maintaining low resistivity. By changing the material parameters of the intermediate layer, the patent achieves both good adhesion and acceptable electrical properties, resolving the contradiction between adhesion improvement and resistivity control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the efficient formation of semiconductor devices with improved adhesion and reduced resistivity, enhancing the performance and yield of semiconductor devices while addressing the complexity and cost-effectiveness challenges in advanced IC manufacturing.
Implementation Method 1
utilizing techniques like CVD, ALD, and photolithography processes
Implementation Method 2
utilizing techniques like CVD, ALD, and photolithography processes
Implementation Method 3
utilizing techniques like CVD, ALD, and photolithography processes
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate stack and a first dielectric layer over the substrate, a source/drain (S/D) region, a contact, and a via. The first dielectric layer is laterally aside and over the gate stack. The S/D region is located in the substrate on sides of the gate stack. The contact penetrates through the first dielectric layer to electrically connect to the S/D region. The via penetrates through a second dielectric layer to connect to the contact. The via includes a conductive layer and an adhesion promoter layer on sidewalls of the conductive layer. The conductive layer is in contact with the contact.