Semiconductor Package Adhesive Layer Layout for Warpage and Stress Relief
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high performance, large capacity, miniaturization, and lightness while maintaining reliability, especially in stacked semiconductor chip configurations.
Innovation Solution
A semiconductor package design that includes a first and second semiconductor chip stacked with an adhesive layer having interposition portions between the chips and a side portion contacting the chip surfaces, surrounded by a molding layer. This design enhances the reliability by minimizing warpage and stress concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor chips are stacked to achieve miniaturization and high capacity, then the package size and capacity are improved, but warpage and stress concentration occur reducing reliability
Solution Approach 1:
The adhesive layer is segmented into two distinct portions: an interposition portion with smaller thickness filling the gap between chips, and a side portion with larger thickness contacting the side surfaces of chips. This segmentation allows differential stress distribution, with the thicker side portion absorbing expansion stress and the thinner interposition portion providing stable bonding, thereby preventing warpage and improving reliability in stacked chip configurations.
Solution Approach 2:
Different regions of the adhesive layer are assigned different thicknesses and functions: the interposition portion has smaller thickness optimized for gap filling and electrical isolation between chips, while the side portion has larger thickness optimized for stress absorption and mechanical support. This local quality differentiation enables the adhesive layer to simultaneously address multiple competing requirements in the stacked chip package.
2Stability of the object's composition
If adhesive layer thickness is increased to reduce stress, then stress concentration is reduced, but warpage increases
Solution Approach 1:
The adhesive layer is divided into portions with different thicknesses: the interposition portion has smaller thickness to minimize warpage contribution, while the side portion has larger thickness to absorb expansion stress. This segmentation resolves the contradiction by placing thicker adhesive material only where stress absorption is needed, rather than uniformly increasing thickness throughout.
Solution Approach 2:
The adhesive layer exhibits local quality variations in thickness: smaller thickness in the interposition region for warpage control, and larger thickness in the side portion for stress reduction. This spatially differentiated thickness distribution allows the system to simultaneously achieve both low warpage and reduced stress concentration.
3Shape
If adhesive layer thickness is decreased to reduce warpage, then warpage is reduced, but stress concentration increases
Solution Approach 1:
The adhesive layer is segmented such that the interposition portion has smaller thickness to reduce warpage, while the side portion has larger thickness to absorb expansion stress. This segmentation allows the system to decrease overall adhesive thickness for warpage control while maintaining sufficient thickness in critical stress-bearing regions.
Solution Approach 2:
The adhesive layer displays local quality differences where the interposition portion has reduced thickness for warpage minimization, and the side portion maintains larger thickness for stress concentration reduction. This localized thickness optimization resolves the contradiction between warpage control and stress management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed semiconductor package design enhances reliability by minimizing warpage and stress concentration, thereby improving the overall performance and durability of the package.
Implementation Method 1
an adhesive layer including an interposition portion and a side portion, the interposition portion between the first semiconductor chip and the second semiconductor chip, and the side portion contacting a side surface of the first semiconductor chip and a side surface of the second semiconductor chip
Data Source
AI summary
A semiconductor package may include a first semiconductor chip, a second semiconductor chip spaced apart from the first semiconductor chip, an adhesive layer including an interposition portion and a side portion, and a molding layer. The molding layer may surround the first semiconductor chip, the second semiconductor chip, and the adhesive layer. The interposition portion may be between the first and second semiconductor chips. The side portion may contact a side surface of the first semiconductor chip and a side surface of the second semiconductor chip. A top surface of the side portion is curved, and an outer side surface of the side portion is flat.