Adiabatic Capacitive Logic Cell Using Variable Resistance
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Solution Overview
Problem
The existing logic cells with variable capacitance capacitors face challenges in manufacturing complexity and large size, limiting their scalability and efficiency in low-power electronic circuits.
Innovation Solution
The design incorporates a logic cell with fixed capacitance and variable resistance elements, including MOS transistors or electromechanical relays, to implement adiabatic logic functions, reducing the need for complex variable capacitance capacitors and enabling easier production and compact integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If variable capacitance capacitors are used in logic cells, then low power consumption is achieved, but manufacturing complexity and device size increase
Solution Approach 1:
The patent replaces electromechanical variable capacitance capacitors with a hybrid system combining fixed capacitance capacitors and electromechanical relays. The relay's mechanical switching action controls resistance states (high/low) to simulate the variable capacitance effect, thereby achieving low power consumption through adiabatic logic while avoiding the manufacturing complexity of variable capacitance capacitors.
Solution Approach 2:
The patent changes the controlling parameter from capacitance variation to resistance variation. By using fixed capacitance capacitors controlled by relays that switch between high and low resistance states, the system achieves the same logical function with simpler, more manufacturable components.
2Use of energy by moving object
If variable capacitance capacitors are used in logic cells, then low power consumption is achieved, but device size increases
Solution Approach 1:
The patent substitutes the large physical structure of variable capacitance capacitors with compact fixed capacitance capacitors combined with small electromechanical relays. The relay's movable arm and contact structure occupy minimal space while achieving the same functional effect, thereby reducing overall device size.
Solution Approach 2:
The patent integrates the fixed capacitance capacitor and electromechanical relay into a compact hybrid structure where the relay's components (coil, arm, contact) are nested within or adjacent to the capacitor structure, maximizing space utilization and minimizing overall device footprint.
3Ease of manufacture
If fixed capacitance capacitors with variable resistance elements are used, then manufacturing ease and size reduction are achieved, but device complexity changes
Solution Approach 1:
The electromechanical relay serves multiple functions: it acts as a variable resistance element, a switch, and a control element simultaneously. This multi-functionality reduces the need for separate components, simplifying the overall device structure despite the hybrid nature of the system.
Solution Approach 2:
The patent merges the fixed capacitance capacitor and electromechanical relay into a single functional unit where the relay's resistance states directly control the capacitor's electrical behavior. This integration creates a compact hybrid structure that is easier to manufacture than separate variable capacitance capacitors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces leakage currents, allows for lower supply voltage amplitudes, and achieves very low power consumption while maintaining efficient logic operations, making it suitable for complex logic circuits with improved manufacturing feasibility and size reduction.
Implementation Method 1
a series association of a second fixed-capacitance capacitor and a first variable resistance element, the first variable resistance element comprising a control electrode connected to a node for applying a first logic input signal of the cell
Implementation Method 2
the cell further comprises a capacitive holding circuit connected between the power node and the floating node of the cell
Implementation Method 3
adiabatic logic cell, comprising: a first fixed-capacitance capacitor connected between a node for applying a periodic variable supply voltage of the cell and a floating node for providing a logic output signal of the cell
Data Source
Figure 1~2
Figure 3
Figure 4~5
AI summary
The present description relates to a logic cell (100), comprising: - a first capacitor (CMIN) connected between a node (a1) for applying a supply voltage (φn) of the cell and a floating node (s1) for supplying a logic output signal (VOUT) of the cell; and - connected in parallel with the first capacitor (CMIN), a series association of a second capacitor (CMAX1) and a first variable resistance element (R1), the first variable resistance element (R1) having a control electrode (G) connected to a node (e1) for applying a first logic input signal (VIN1) of the cell.