Adiabatic Stepwise Clock Driver Using Isolated MIM Capacitors
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Solution Overview
Problem
Conventional clock circuitry designs require multiple voltage supplies and large MOS-based capacitors, leading to inefficient use of silicon area and impractical implementation due to their large footprint.
Innovation Solution
The implementation of an adiabatic stepwise clocking architecture with selectively switched stages, using metal-insulator-metal (MIM) capacitors as auxiliary tank capacitors that are physically and electrically isolated, to reduce the area impact and enhance efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple voltage supplies and voltage regulators are used in clock circuitry, then clock signal generation capability is improved, but silicon area occupied increases excessively
Solution Approach 1:
The patent combines multiple voltage supply functions into a single voltage supply by using an adiabatic clock driver that can generate multiple clock signals with different voltage levels from one supply. The clock driver integrates the functionality of multiple voltage regulators and clock generators into a unified circuit structure, eliminating the need for separate voltage supplies and regulators for each clock tree.
Solution Approach 2:
The adiabatic clock driver is designed as a universal circuit that can simultaneously generate multiple clock signals with different voltage levels and frequencies to drive different clock trees. This multi-functional circuit replaces multiple specialized circuits (multiple voltage regulators, multiple clock generators), reducing overall silicon area while maintaining comprehensive clock distribution capability.
2Stability of the object's composition
If large MOS based capacitors are used in clock circuitry, then clock signal stability is improved, but silicon area occupied increases excessively
Solution Approach 1:
The patent changes the capacitance value parameter dynamically during clock signal generation. The adiabatic clock driver adjusts the effective capacitance in different operating phases and for different clock outputs, using smaller capacitors than traditional designs would require. This parameter adjustment allows stable clock signal generation with reduced capacitor sizes, thereby reducing silicon area.
Solution Approach 2:
The patent employs a composite capacitance structure combining MOS capacitors and MIM (Metal-Insulator-Metal) capacitors. This composite approach leverages the advantages of both capacitor types to achieve the required clock signal stability with smaller total capacitance values, reducing the silicon area occupied by capacitive elements.
3Adaptability or versatility
If conventional clock circuit designs are implemented, then clock distribution function is achieved, but circuit complexity and area efficiency are worsened
Solution Approach 1:
The patent segments the clock distribution system into hierarchical levels with a single adiabatic clock driver at the top generating master clock signals, which are then distributed to multiple clock trees. This segmentation allows one complex circuit to control multiple simpler clock distribution networks, reducing overall system complexity while maintaining comprehensive clock distribution functionality.
Data Source
AI summary
Various implementations described herein are directed to a device having a clock driver that provides an adiabatic stepwise clock signal via an output node, and the clock driver may be coupled between a supply voltage and ground. Also, the device may have selectively switched stages with each selectively switched stage having a capacitor and a transistor coupled in series between the output node and ground. In some instances, each capacitor may refer to an auxiliary tank capacitor that is electrically isolated from each other auxiliary tank capacitor.