Adiabatic Flip-Flop Bennett Clocking for Energy Recovery
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Solution Overview
Problem
Modern microprocessors are limited by heat generation, with CMOS circuits dissipating energy as heat during switching, capping their speed at 4 GHz since 2004, and sequential elements have not been effectively implemented using adiabatic logic.
Innovation Solution
Adiabatic computing is implemented using split-rail charge recovery logic (SCRL) with Bennett clocking, incorporating adiabatic flip-flops and memory designs that minimize energy dissipation by employing phased clocks and energy recovery stages in master-follower flip-flops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional CMOS circuits are used for computing operations, then device performance can be maintained at current levels, but heat generation increases and speed is capped at 4 GHz
Solution Approach 1:
The patent implements energy recovery circuits that capture and store the energy normally dissipated as heat during CMOS switching operations. Recovery capacitors are charged during logic transitions and then discharged to replenish energy in subsequent cycles, effectively recovering what would otherwise be wasted energy and reducing overall heat generation while enabling higher operating speeds
2Productivity
If traditional CMOS switching operations are performed, then logic operations can be executed, but energy is dissipated as heat during each switching event
Solution Approach 1:
The patent implements energy recovery circuits that capture and store the energy normally dissipated as heat during CMOS switching operations. Recovery capacitors are charged during logic transitions and then discharged to replenish energy in subsequent cycles, effectively recovering what would otherwise be wasted energy and reducing overall heat generation while enabling higher operating speeds
3Loss of energy
If adiabatic logic is used to reduce energy dissipation, then heat generation decreases, but sequential elements have not been effectively implemented
Solution Approach 1:
The patent divides the sequential element into distinct adiabatic stages including master latch, isolation latch, and output latch, each operating on phased clock signals. This segmentation allows each stage to be optimized for adiabatic operation while maintaining proper sequential functionality through controlled signal propagation between stages
Solution Approach 2:
The patent employs multi-phase periodic clock signals to control the operation of adiabatic sequential elements. Different phases of the clock cycle enable different stages of the flip-flop to operate in sequence, ensuring proper timing and signal propagation while maintaining adiabatic switching conditions that minimize energy dissipation
Data Source
AI summary
A method including, during time period A, in a computer storage element having first and second power inputs separated by an array of transistors configured for storing a computer bit of data, moving an input of the array of transistors a logic value “1” or “0” a master latch, during time period B, recovering at least a portion of energy comprising the input with a first clock, during a time period C, moving the input in the master latch to an isolation stage, during time period D, recovering at least a portion of energy comprising the input from the isolation stage with a second clock, during time period E, recovering at least a portion of energy comprising the input from a follower latch with a third clock, and during time period F, moving at least a portion of the input from the isolation stage to the follower latch.