Adiabatic Logic-in-Memory Circuit With Energy-Recovering PCSA
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Solution Overview
Problem
CMOS logic design faces high power leakage issues as the technology node shrinks below 100 nm, and while Logic-In-Memory (LiM) circuits with MTJ cells reduce leakage power, they require high supply voltages, leading to inefficiency and potential incorrect operations when scaling down.
Innovation Solution
Adiabatic Logic-In-Memory (ALiM) architecture is introduced, which uses a multi-phase clock signal to slowly charge and discharge load capacitors, recovering energy and minimizing both dynamic power consumption and power leakage in CMOS/MTJ circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional PCSA based CMOS/MTJ circuits are used, then logic functionality is achieved, but high power consumption and high energy dissipation occur due to abrupt charging and discharging of capacitors
Solution Approach 1:
The patent implements a multi-phase clock signal system with four distinct phases (phi1, phi2, phi3, phi4) that periodically control the charging and discharging of capacitors. This periodic action replaces the conventional single-phase abrupt switching, allowing energy to be recovered during specific phases (e.g., phi3 recovers energy from phi1, phi4 recovers from phi2) rather than being dissipated, thereby reducing overall power consumption and energy loss
Solution Approach 2:
The patent recovers energy that would otherwise be discarded during capacitor discharge operations. The energy recovery mechanism captures the energy stored in capacitors during the evaluation phase and returns it to the power supply or stores it for reuse during subsequent precharge phases, transforming what was previously wasted energy into a reusable resource and significantly reducing power consumption
2Use of energy by moving object
If supply voltage is scaled down to reduce power consumption, then energy efficiency improves, but leakage power increases and circuit operation becomes unreliable
Solution Approach 1:
The patent changes the temporal parameters of voltage application by using multi-phase clock signals with different duty cycles and timing relationships. Instead of a single continuous voltage level, the system applies voltage in controlled phases with specific rise and fall times, allowing the circuit to operate reliably at lower supply voltages by extending the time available for charge/discharge operations and reducing leakage effects
3Quantity of substance
If CMOS technology node is scaled down to 100 nm or below to increase integration density, then device density improves, but power leakage becomes a major concern
Solution Approach 1:
The patent maintains continuous useful action by keeping capacitors charged during idle periods through the multi-phase clocking mechanism. Instead of allowing capacitors to discharge completely and then recharge (which causes leakage), the system continuously recycles charge among phases, ensuring that energy remains stored and useful throughout the operating cycle, thereby reducing leakage power in scaled-down CMOS nodes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ALiM architecture achieves significant energy and power savings, with simulations showing 62% energy and 50% power savings compared to conventional PCSA based circuits, while also reducing the number of devices and area, making it suitable for ultra-low-power portable devices.
Implementation Method 1
Adiabatic Logic-In-Memory (ALiM) architecture is introduced, which uses a multi-phase clock signal to slowly charge and discharge load capacitors, recovering energy
Data Source
AI summary
An adiabatic logic-in-memory based complementary metal-oxide-semiconductor/magnetic-tunnel-junction (ALiM CMOS/MTJ) circuit utilizes an adiabatic logic based pre-charged sense amplifier (PCSA) to recover energy from its output load capacitors. The ALiM CMOS/MTJ includes a non-volatile magnetic-tunnel-junction (MTJ) based memory. The ALiM CMOS/MTJ also includes a dual rail complementary metal-oxide-semiconductor (CMOS) logic that performs logic operations in association with the MTJ, and thereby generates logic outputs based on logic inputs. The ALiM CMOS/MTJ also includes the adiabatic PCSA, which is operatively coupled to the dual rail CMOS logic. The adiabatic logic based PCSA includes PCSA circuitry for which an input is a multi-phase power clock, and a charge recovery circuit having the output load capacitors. The charge recovery circuit is operatively coupled to the PCSA circuitry such that the ALiM CMOS/MTJ circuit uses the power clock to recover energy from the output load capacitors.