Adjacent 2-Bit Error Correction Using H-Matrix Syndrome Links

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Solution Overview

Problem

Existing error correction methods, particularly those using Bose-Chaudhuri-Hocquenghem (BCH) codes, are inefficient in determining the zeroes of the locator polynomial, leading to high processing time for error correction.

Innovation Solution

A method is proposed that uses an H-matrix to process errors in a sequence of bits, where an error syndrome is determined and linked with components of the H-matrix, allowing for the correction of adjacent 2-bit errors by inverting error syndrome components based on the H-matrix columns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the Chien algorithm is used to determine zeroes of the locator polynomial, then error correction capability is achieved, but processing time becomes excessively long

Engineering Contradiction:
Improveerror correction capabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the error correction problem by distinguishing between adjacent 2-bit errors and other error patterns. By checking specific syndrome conditions (s0 = s2 and s1 = s3 for adjacent errors), the algorithm can quickly identify and correct adjacent 2-bit errors without performing the complete time-consuming Chien algorithm, thus reducing overall processing time while maintaining error correction capability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies partial action by implementing a simplified correction approach for specific error cases (adjacent 2-bit errors) rather than applying the full Chien algorithm to all error patterns. This partial correction method checks only necessary syndrome components and applies correction only when specific conditions are met, significantly reducing processing time for the common case of adjacent errors while still providing comprehensive error correction through the full algorithm when needed

Inventive Principle:
Principle #16Partial or excessive action

2Adaptability or versatility

If general error correction methods are used, then all types of errors can be corrected, but correction speed is reduced

Engineering Contradiction:
Improveerror type coverageVSAvoidcorrection speed
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent applies local quality by implementing different correction strategies for different error patterns. For adjacent 2-bit errors, it uses a specialized fast correction method that checks syndrome relationships and applies direct correction. For other error patterns, it falls back to the general Chien algorithm. This localized optimization maintains versatility in handling all error types while achieving high-speed correction for the specific case of adjacent errors

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12316346B2Error processing and correction of adjacent 2-bit errors
Publication Date: 2025.05.27 INFINEON TECHNOLOGIES AG
  • US12316346B2 patent drawing
  • US12316346B2 patent drawing
  • US12316346B2 patent drawing

AI summary

What is proposed is a solution for processing errors in a sequence of bits, wherein the sequence of bits, in the error-free case, forms a codeword of an error code, wherein the error code is based on an H-matrix or is able to be determined thereby, wherein an error syndrome is determined for the sequence of bits, wherein a link is determined between components of the error syndrome and parts of the H-matrix, and wherein two adjacent bits in the sequence of bits are corrected if the link adopts a predefined value.