Adjacent Circuit Interconnects for Wafer Test Efficiency
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Solution Overview
Problem
Current methods for testing unsingulated dice on wafers are inefficient, costly, and prone to damage, as they require expensive mechanical probing, additional wafer processing, or excessive use of wafer area, and often necessitate separate JTAG interfaces that are not scalable.
Innovation Solution
A system and method that connects test data, clock, and mode select signals between adjacent circuits using a test data interconnect, test clock interconnect, and test mode select interconnect, allowing for efficient testing via a single contact region, eliminating the need for BIST circuitry, widened scribe lanes, and multiple JTAG interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If mechanical probing is used to test unsingulated dice, then testing can be performed, but the probing is slow and requires expensive mechanical mechanisms
Solution Approach 1:
The patent replaces the mechanical probing system with an electrical interconnect system. Test data, clock, and mode select signals are transmitted through conductive interconnects between adjacent dice, eliminating the need for mechanical probe positioning while enabling parallel testing of multiple dice simultaneously.
Solution Approach 2:
The patent combines multiple testing functions into a unified interconnect system. The same physical interconnects carry test data, clock signals, and mode select signals, allowing coordinated testing of multiple dice through shared signal paths rather than separate mechanical probes for each die.
2Reliability
If mechanical probing is used to test unsingulated dice, then testing can be performed, but expensive mechanical mechanisms are required to step and position the probe
Solution Approach 1:
The patent replaces the mechanical probing system with an electrical interconnect system. Test data, clock, and mode select signals are transmitted through conductive interconnects between adjacent dice, eliminating the need for mechanical probe positioning while enabling parallel testing of multiple dice simultaneously.
3Reliability
If probing is used to test unsingulated dice, then testing can be performed, but the probing step can damage the die pads
Solution Approach 1:
The patent replaces the mechanical probing system with an electrical interconnect system. Test data, clock, and mode select signals are transmitted through conductive interconnects between adjacent dice, eliminating the need for mechanical probe positioning while enabling parallel testing of multiple dice simultaneously.
4Productivity
If die sizes shrink and pads are positioned closer together, then more dice can be produced on a wafer, but probing becomes more difficult and expensive
Solution Approach 1:
The patent replaces the mechanical probing system with an electrical interconnect system. Test data, clock, and mode select signals are transmitted through conductive interconnects between adjacent dice, eliminating the need for mechanical probe positioning while enabling parallel testing of multiple dice simultaneously.
5Productivity
If BIST circuitry is added to each die for self-testing, then testing can be performed without probing, but BIST circuitry takes up die area
Solution Approach 1:
The patent creates a universal test interconnect system that serves multiple dice simultaneously. The same interconnect infrastructure carries test signals to and from multiple adjacent dice, eliminating the need for dedicated BIST circuitry in each die while maintaining efficient testing capability across the entire wafer.
6Reliability
If scribe lanes are widened to allow test probe points, then testing can be performed, but the widening reduces the number of dice that can be produced on a wafer
Solution Approach 1:
The patent merges the test signal paths through the existing scribe lane infrastructure without requiring widening. Test data, clock, and mode select signals are routed through interconnects that utilize the available space in standard scribe lanes, enabling testing while maintaining maximum wafer capacity for dice production.
7Reliability
If an overlying layer of semiconductor material with test circuitry is processed, then testing can be performed, but additional wafer processing steps are required and the underlying dice could be damaged during removal
Solution Approach 1:
The patent extracts the test functionality from separate processing layers and integrates it directly into the dice interconnect structure. Test signals are transmitted through interconnects formed as part of the standard dice fabrication process, eliminating the need for separate overlying test layers and their associated deposition and removal steps.
8Reliability
If separate JTAG interfaces are provided for each die, then testing can be performed, but more JTAG interfaces than a tester can accommodate are required
Solution Approach 1:
The patent merges multiple JTAG test interfaces into a unified interconnect system. Test data, clock, and mode select signals are multiplexed through shared interconnects that serve multiple adjacent dice, allowing a single tester to control and test multiple dice simultaneously through fewer physical interfaces.
Solution Approach 2:
The patent creates a universal test interconnect system that serves multiple dice simultaneously. The same interconnect infrastructure carries test signals to and from multiple adjacent dice, eliminating the need for dedicated BIST circuitry in each die while maintaining efficient testing capability across the entire wafer.
Data Source
AI summary
A system for, and method of, testing a plurality of circuits, which may be unsingulated die on a wafer. In one embodiment, the system includes: (1) a test data interconnect that connects a test data output of a first circuit directly to a test data input of a second circuit located adjacent to the first circuit, (2) a test clock interconnect that connects a test clock output of the first circuit directly to a test clock input of the second circuit, (3) a test mode select interconnect that connects a test mode select output of the first circuit directly to a test mode select input of the second circuit and (4) a contact region coupled to provide test data, a test clock signal and a test mode select signal respectively to the test data interconnect, the test clock interconnect and the test mode select interconnect.