Adjacent MOL Via Structure for Scaled Bit-Line Contact Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a continued desire to further reduce the size of semiconductor structures, particularly field-effect transistors (FETs), to achieve increased performance at lower power levels and lower costs, beyond the capabilities of existing miniaturization techniques such as fin-shaped channels and stacked nanosheet channels.
Innovation Solution
The formation of a via adjacent a middle-of-line (MOL) contact in semiconductor devices, where a conductive via is disposed along the side of the contact and isolated by a dielectric liner layer, which also contacts a bit-line, allowing for further miniaturization and improved electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional miniaturization techniques (fin-shaped channels, stacked nanosheet channels) are used, then device size is reduced, but further scaling is limited and electrical isolation becomes more difficult
Solution Approach 1:
A dielectric liner layer is introduced as an intermediary between the MOL contact and the via fill material. This liner layer provides electrical isolation and prevents unwanted interactions between the contact and via materials, enabling further miniaturization while maintaining electrical integrity. The liner acts as a mediator that resolves the conflict between reducing device size and maintaining reliable electrical isolation.
Solution Approach 2:
The via structure is segmented into distinct functional layers: the MOL contact, the dielectric liner layer, and the via fill material. This segmentation allows each component to be optimized independently - the contact for electrical connection, the liner for isolation, and the via fill for structural support and additional conduction paths - thereby enabling continued scaling while maintaining electrical isolation.
2Productivity
If device size is reduced further, then performance increases and device area footprint decreases, but manufacturing complexity increases
Solution Approach 1:
The dielectric liner layer is formed in advance, before the via fill material is deposited. This preliminary action of lining the via with dielectric material beforehand simplifies the subsequent manufacturing steps by providing a pre-prepared structure that guides the via fill deposition and ensures proper electrical isolation from the start, rather than requiring complex post-processing to achieve isolation.
Solution Approach 2:
The dielectric liner layer serves multiple functions simultaneously: it provides electrical isolation between the MOL contact and via fill, acts as a barrier to prevent material diffusion, provides a planar surface for via fill deposition, and contributes to the mechanical stability of the via structure. This multi-functionality reduces the need for additional separate structures, thereby managing complexity while enabling further miniaturization.
Data Source
AI summary
A semiconductor device comprises a contact electrically connected to a source/drain region of a transistor and to a gate region of the transistor. A via is disposed along a side of the contact, wherein the via comprises a conductive material. A dielectric liner layer is disposed around at least a portion of the conductive material. The dielectric liner layer electrically isolates the contact from the conductive material, and the via contacts a bit-line.