Adjacent Row Mapping for Accurate DRAM Row-Hammer Refresh

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Solution Overview

Problem

Conventional approaches to protecting memory devices from row-hammer attacks are inefficient or ineffective, particularly when addressing non-adjacent neighboring rows, leading to potential data manipulation and security vulnerabilities.

Innovation Solution

Implementing a physically adjacent row mapping table to identify and refresh adjacent rows in volatile memory, using a non-volatile memory to store the mapping table and applying a security protocol for access, thereby reducing computational complexity and improving accuracy in identifying neighboring rows subject to attacks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional dummy reads are performed to neighboring rows using address incrementing/decrementing, then row-hammer protection is attempted, but addresses of non-adjacent rows are accessed resulting in ineffective protection and computational complexity

Engineering Contradiction:
Improverow-hammer protection effectivenessVSAvoidcomputational complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A mapping table is introduced as an intermediary data structure that stores the actual physical addresses of neighboring rows. Instead of directly computing neighboring addresses through incrementing/decrementing operations, the system uses this mapping table to look up and retrieve the correct physical addresses, thereby simplifying the computational process while ensuring accurate identification of adjacent rows for effective row-hammer protection.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The mapping table is pre-computed and stored before the row-hammer protection operation is executed. The physical addresses of neighboring rows are determined in advance and stored in the mapping table, allowing the protection mechanism to simply perform lookups during operation rather than performing complex address calculations in real-time, thus reducing computational complexity.

Inventive Principle:
Principle #10Preliminary action

2Ease of operation

If address incrementing/decrementing is used to identify neighboring rows, then the process is simple, but non-consecutive addresses result in accessing non-adjacent rows reducing protection accuracy

Engineering Contradiction:
Improveaddress calculation simplicityVSAvoidneighboring row identification accuracy
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The mapping table serves as an intermediary that bridges the simple address incrementing/decrementing operation with the accurate identification of physical neighboring rows. The mapping table stores the correct physical addresses corresponding to logical neighboring rows, allowing the system to maintain simple operational logic while achieving precise row identification for effective protection.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If repeated accesses to target row are attempted for data manipulation, then indirect modification is achieved, but security vulnerabilities arise from potential data manipulation

Engineering Contradiction:
Improvedata access flexibilityVSAvoidsecurity vulnerability
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The system performs preliminary protective actions by identifying and refreshing neighboring rows before potential row-hammer attacks can successfully manipulate data. By proactively refreshing the neighboring rows that are susceptible to electrical coupling effects, the system prevents the harmful data manipulation from occurring in the first place, thereby addressing security vulnerabilities while maintaining data access flexibility.

Inventive Principle:
Principle #9Preliminary anti-action

Data Source

PatentUS20260063709A1Row-hammer condition mitigation using a physically adjacent row mapping table
Publication Date: 2026.03.05 QUALCOMM INC
  • US20260063709A1 patent drawing
  • US20260063709A1 patent drawing
  • US20260063709A1 patent drawing

AI summary

In some aspects, an apparatus includes a processing system that includes one or more processors and one or more memories coupled to the one or more processors. The processing system is configured to send one or more memory access commands to a volatile memory. The one or more memory access commands are associated with a first address. The processing system if further configured to access, based on detecting a row-hammer condition associated with the one or more memory access commands, a physically adjacent row mapping table to determine at least a second address. The first address and the second address correspond to physically adjacent rows within the volatile memory. The processing system if further configured to send one or more row refresh commands to the volatile memory based on the row-hammer condition. The one or more row refresh commands are associated with at least the second address.