Adjacent Structure Isolation Layout for Scaled FinFET and GAA
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing low-cost, high-performance, and low-power integrated circuits due to increased complexity in scaling down semiconductor IC dimensions, which affects gate control and introduces short-channel effects in FinFETs and GAA transistors.
Innovation Solution
The implementation of a Continuous Poly on Diffusion Edge (CPODE) process with shallow vertically-extending isolation structures and laterally-extending isolation layers to reduce parasitic capacitance and leakage current, combined with a method for fabricating multi-gate devices like FinFETs and GAA transistors using a CMOS technology flow, including epitaxial growth, patterning, and replacement metal gate processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional scaling down of semiconductor IC dimensions is used, then production efficiency is improved and costs are lowered, but manufacturing complexity increases and gate control deteriorates
Solution Approach 1:
The isolation structure is segmented into two distinct parts: a shallow vertically-extending isolation structure (trench filled with dielectric material) and a laterally-extending isolation layer positioned at a different elevation. This segmentation allows each component to address specific isolation needs independently, improving manufacturing feasibility while maintaining electrical isolation effectiveness in scaled-down devices.
Solution Approach 2:
The patent transitions from traditional single-level isolation to a multi-dimensional isolation architecture. The laterally-extending isolation layer is positioned at a different elevation (z-direction) than the shallow vertically-extending isolation structure, creating a three-dimensional isolation system that provides superior electrical isolation without increasing planar footprint, thus enabling continued scaling.
2Productivity
If conventional scaling down of semiconductor IC dimensions is used, then production efficiency is improved and costs are lowered, but gate control and short-channel effects deteriorate
Solution Approach 1:
The dual-component isolation structure segments the isolation function into vertical and lateral components, allowing precise control of the electrical environment around the gate. The shallow vertically-extending isolation structure provides immediate electrical isolation, while the laterally-extending isolation layer extends isolation coverage, collectively improving gate control in scaled devices.
Solution Approach 2:
The isolation layer acts as an intermediary element between adjacent semiconductor structures, positioned at a different elevation to provide electrical isolation without interfering with the primary device operation. This intermediary structure mitigates short-channel effects by controlling the electrical environment, enabling continued scaling while maintaining reliability.
3Device complexity
If traditional isolation structures are used, then manufacturing is simpler, but parasitic capacitance and leakage current increase
Solution Approach 1:
The isolation function is segmented into two components operating at different elevations: the shallow vertically-extending isolation structure provides primary electrical isolation, while the laterally-extending isolation layer extends isolation coverage and reduces parasitic capacitance by increasing separation distance. This segmentation effectively reduces leakage current and parasitic capacitance without excessive complexity.
Solution Approach 2:
By introducing the laterally-extending isolation layer at a different elevation (z-direction), the patent creates a three-dimensional isolation system that reduces parasitic capacitance more effectively than planar isolation structures. The vertical separation increases the distance between conductive elements, thereby reducing capacitive coupling and leakage current.
Data Source
AI summary
Provided are semiconductor devices with isolation structures and methods for fabricating such devices. An exemplary method includes forming an isolation layer over a semiconductor material; forming source/drain regions over the isolation layer; removing a selected gate structure, wherein removing the selected gate structure forms a trench in the semiconductor material; and forming an isolation structure in the trench.