Word Line Voltage Compensation for Parasitic Cell Disturbance
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Solution Overview
Problem
Undesired voltage disturbances occur between target and adjacent memory cells due to parasitic capacitors during memory operations, leading to erroneous memory operations if not compensated for.
Innovation Solution
The row decoder applies compensatory voltages to adjacent word lines to reduce voltage disturbances by inducing parasitic capacitance with an opposite effect, using reference and compensatory voltages to mitigate the impact of undesired parasitic capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sensing or programming targeted memory cells is performed, then memory operations can be executed, but voltage disturbances occur in untargeted adjacent memory cells due to parasitic capacitors
Solution Approach 1:
The patent applies preliminary anti-action by providing compensatory voltages to adjacent word lines before and during the sensing or programming operation. These compensatory voltages are specifically designed to counteract the voltage disturbances that would otherwise be induced in untargeted memory cells by parasitic capacitors, thereby preventing charge level changes in adjacent cells while allowing the target memory cell operation to proceed
Solution Approach 2:
The patent implements the counterweight principle by introducing compensatory voltages that act as an opposing force to the harmful voltage disturbances. The compensatory voltages are applied to adjacent word lines with polarities and magnitudes specifically chosen to balance and neutralize the parasitic capacitor effects, creating a counteracting influence that protects untargeted memory cells from charge disturbances
2Reliability
If compensatory voltages are applied to adjacent word lines, then voltage disturbances are reduced, but device complexity increases due to additional voltage control requirements
Solution Approach 1:
The patent applies universality by designing the row decoder circuit to perform multiple functions: it simultaneously selects the target word line and provides compensatory voltages to adjacent word lines. The same decoder infrastructure that controls normal memory operations is extended to also handle the compensatory voltage generation and distribution, thereby reducing the need for separate dedicated compensation circuitry and minimizing additional complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory cell sensing and programming reliability with reduced error rates by minimizing voltage disturbances and improving operational accuracy.
Implementation Method 1
If not compensated for, sensing or programming targeted memory cells of the memory device may disturb a charge level of one or more untargeted adjacent memory cells
Data Source
AI summary
A memory cell may include a capacitor and a switch. Accessing the memory cell in a memory array of a memory device may include applying a word line voltage to the switch to electrically couple the capacitor to a data line. However, if not compensated for, applying the word line voltage may induce undesired voltages on adjacent memory cells of the memory arrays. Systems and methods are described to reduce an effect of one or more parasitic capacitors causing the undesired voltage disturbance. For example, the memory array may provide compensatory voltages to adjacent word lines of a target word line to compensate for such undesired parasitic capacitors. Accordingly, an undesired voltage disturbance of the memory cells may be reduced.