Adjoined Via Structures for Precise 3D Semiconductor Bonding
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Solution Overview
Problem
Conventional methods for forming through-silicon vias (TSVs) in 3D semiconductor devices face challenges in achieving high alignment precision, reducing thermal budget, and minimizing parasitic capacity and non-uniformities while simplifying wiring and reducing fabrication costs.
Innovation Solution
The method involves bonding semiconductor structures with adjoined via structures, where via portions are formed and bonded in the same fabrication operations as bonding contacts, allowing for staggered profiles and hybrid bonding to enhance alignment precision and reduce thermal influence, parasitic capacity, and fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional through-silicon via (TSV) methods are used in 3D semiconductor devices, then via structures can be formed to enable vertical interconnect, but alignment precision is difficult to achieve and thermal budget is increased
Solution Approach 1:
The via structure is divided into multiple segments: a first via portion formed in the first semiconductor structure, and a second via portion formed in the second semiconductor structure. These segments are bonded together at the bonding interface to form a continuous vertical interconnect. This segmentation allows each via portion to be formed independently with relaxed alignment tolerances, while still achieving the overall via function.
Solution Approach 2:
The invention transitions from forming complete through-silicon vias in a single substrate to forming via portions in separate substrates that are then joined in the vertical dimension. This dimensional approach to via formation enables independent optimization of each via portion and reduces the thermal budget by avoiding high-temperature processing of the entire via structure in one step.
2Reliability
If conventional TSV methods are used, then via structures can be formed, but parasitic capacity and non-uniformities increase
Solution Approach 1:
By segmenting the via structure into portions formed in separate semiconductor structures, each portion can be independently optimized for uniformity and low parasitic capacity. The bonding interface joins these optimized segments, preserving their individual advantages while achieving the complete via function.
3Ease of manufacture
If conventional TSV methods are used, then via structures can be formed, but wiring complexity and fabrication costs increase
Solution Approach 1:
The via structure is segmented into portions that are formed as part of the respective semiconductor structures during their fabrication processes, rather than requiring separate via formation and wiring steps. This integration simplifies the overall wiring complexity and reduces fabrication costs by eliminating redundant processing steps.
Solution Approach 2:
The via formation process is merged with the semiconductor structure fabrication process. The via portions are formed concurrently with the bonding contacts during the respective structure fabrications, and then automatically aligned and bonded together, eliminating separate via alignment and bonding steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies wiring, reduces the overall thickness of semiconductor structures, enhances alignment precision, minimizes thermal and non-uniformity issues, and lowers fabrication costs, achieving efficient electrical signal transmission between bonded semiconductor structures.
Implementation Method 1
a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface, and the first via structure is in contact with the second via structure
Data Source
AI summary
Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first bonding layer having a plurality of first bonding contacts, and a first via structure extending vertically through the first bonding layer and into the first semiconductor structure. The second semiconductor structure includes a second bonding layer having a plurality of second bonding contacts, and a second via structure extending vertically through the second bonding layer and into the second semiconductor structure. The first bonding contacts are in contact with the second bonding contacts at the bonding interface, the first via structure is in contact with the second via structure, and sidewalls of the first via structure and the second via structures have a staggered profile at the bonding interface.