Adjunct Processor Queue Interrupt Mechanism

The patent implements an interrupt mechanism that provides active feedback to the central processor when replies become available in the adjunct processor queue. Instead of the central processor continuously polling to check for replies, the system generates an interrupt signal that actively notifies the central processor of reply availability. This feedback mechanism eliminates blind polling while maintaining accurate detection of reply availability, thereby resolving the contradiction between measurement precision and productivity.

The adjunct processor autonomously determines when replies are available and generates interrupts accordingly, without requiring the central processor to continuously query. The system serves itself by having the adjunct processor monitor its own queue status and initiate notification when appropriate, eliminating the need for external polling while maintaining accurate reply availability detection.

The patent replaces periodic polling initiated by interval timers with event-driven interrupt generation. Instead of checking for replies at fixed time intervals regardless of actual reply availability, the system generates interrupts only when replies actually become available in the queue. This eliminates periodic checks that occur at inappropriate times, reducing unnecessary operations while maintaining accurate detection of reply availability.

The adjunct processor performs preliminary monitoring of its own queue status and proactively generates interrupts before the central processor would need to poll. By anticipating reply availability and notifying the central processor in advance, the system eliminates the need for subsequent polling operations, reducing time loss while maintaining detection accuracy.