Adjustable Bias Signal Circuit for Low-Speed Clock Power Saving
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Solution Overview
Problem
Existing clock circuits in memory systems have fixed power consumption, which is not optimized for power efficiency, especially in low-speed modes where reduced power is feasible without compromising stability.
Innovation Solution
A circuit for generating a bias signal that can be flexibly adjusted by connecting a second subcircuit in parallel with a first subcircuit, using a switch element controlled by a low-speed mode control signal, allowing the bias voltage to be raised and power consumption to be reduced by controlling the clock calibration circuit's power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock circuit uses fixed power consumption to maintain stability, then clock stability is improved, but power efficiency deteriorates
Solution Approach 1:
The patent applies dynamics by making the bias voltage adjustable rather than fixed. The bias circuit can dynamically change the bias voltage level based on operating conditions (high-speed or low-speed mode), allowing the clock circuit to adapt its power consumption while maintaining stability in each mode. This resolves the contradiction by enabling both stability (through controlled bias) and power efficiency (through mode-dependent voltage adjustment).
Solution Approach 2:
The patent changes the bias voltage parameter to resolve the contradiction. By adjusting the bias voltage from a fixed value to a variable parameter with at least two different levels (first bias voltage for high-speed mode, second bias voltage for low-speed mode), the system can optimize power efficiency while maintaining clock stability appropriate for each operating mode.
2Reliability
If the bias voltage is increased to maintain clock stability, then clock stability is improved, but power consumption increases
Solution Approach 1:
The bias circuit dynamically adjusts the bias voltage based on the operating mode. In low-speed mode, it applies a higher second bias voltage to maintain stability at lower power, while in high-speed mode, it uses a lower first bias voltage optimized for speed. This dynamic adjustment resolves the contradiction by matching bias voltage to operational requirements rather than using a consistently high voltage.
Solution Approach 2:
The patent changes the bias voltage parameter to have at least two different values depending on operating mode. This parameter change allows the system to optimize the trade-off between stability and power consumption for each mode, rather than being constrained to a single high voltage setting that would increase overall power consumption.
3Speed
If the clock circuit is optimized for high-speed operation, then processing speed is improved, but power consumption increases
Solution Approach 1:
The bias circuit provides dynamic bias voltage adjustment based on the required operating mode. When high-speed operation is needed, it supplies the first bias voltage optimized for speed. When low-speed operation suffices, it switches to the second bias voltage that reduces power consumption. This dynamic adaptation resolves the contradiction by allowing speed optimization only when necessary.
Solution Approach 2:
The patent implements parameter changes by providing at least two different bias voltage levels. The bias circuit can switch between the first bias voltage (for high-speed mode) and the second bias voltage (for low-speed mode), allowing the system to change operational parameters to match performance requirements and minimize power consumption accordingly.
Data Source
AI summary
Provided are a circuit for generating a bias signal and a clock input circuit for applying the circuit for generating a bias signal. The circuit for generating a bias signal includes: a first subcircuit, a first terminal of the first subcircuit being connected to a power supply voltage by means of a first node, a second terminal of the first subcircuit being connected to a current stabilization circuit by means of a second node, the first subcircuit being configured to generate a bias signal and output the bias signal by means of the second node, and the current stabilization circuit being configured to provide a constant current to the second node; and a second subcircuit, two terminals of the second subcircuit being respectively connected to the first node and the second node, the second subcircuit including a first resistor element and a first switch element connected in series.