Adjustable Bit Length Counter for Asynchronous Serial Data Transfer
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Solution Overview
Problem
Existing asynchronous serial data transfer systems face limitations in precision due to fixed bit length increments of 8 or 16 oscillator cycles, leading to errors in setting desired transfer rates, especially at specific oscillator frequencies, which are not tolerable in many applications.
Innovation Solution
An integrated circuit with an adjustable bit length counter and prescaler, allowing variable adjustment of the number of clock cycles, enabling precise bit length adjustment in oscillator clock increments, and potentially increasing the sampling frequency for quicker synchronization character detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fixed bit length counter with a fixed number of clock cycles per bit (e.g., 8 or 16) is used, then the device complexity is reduced and ease of manufacture is improved, but the measurement precision of the transfer rate deteriorates due to limited adjustability in oscillator clock increments
Solution Approach 1:
The patent applies the dynamics principle by making the bit length counter adjustable rather than fixed. The counter can be programmed with different values to change the number of clock cycles per bit dynamically, allowing precise adaptation to different transfer rates while maintaining a manageable device structure through systematic design.
Solution Approach 2:
The invention implements parameter changes by allowing the bit length counter value to be modified based on the desired transfer rate. The system calculates the appropriate counter value from the transfer rate and oscillator frequency, then programs the counter accordingly, enabling precise control of the bit time parameter without increasing device complexity.
2Adaptability or versatility
If the number of clock cycles per bit is fixed at 8 or 16, then the device complexity is minimized, but the productivity of setting different transfer rates deteriorates due to large increment steps
Solution Approach 1:
The patent makes the bit length counter dynamic and programmable, allowing it to adapt to different transfer rate requirements. The counter value is calculated based on the desired transfer rate and oscillator frequency, enabling fine-grained adjustment without requiring complex hardware structures.
Solution Approach 2:
The invention creates a universal bit length counter that can serve multiple transfer rate requirements through a single programmable structure. The same counter hardware can be configured for different bit lengths by loading different values, eliminating the need for multiple fixed counters and improving adaptability.
3Measurement precision
If a fixed prescaler with integer divisors is used, then the ease of manufacture is improved, but the measurement precision of the sampling clock deteriorates due to limited division ratios
Solution Approach 1:
The patent applies parameter changes by making the prescaler divisor programmable rather than fixed. The divisor value is calculated based on the desired sampling clock frequency and the system clock frequency, allowing precise adjustment of the sampling rate while implementing the prescaler through standard digital logic components.
Data Source
AI summary
An integrated circuit for an asynchronous serial data transfer comprises a sampler to sample the asynchronous serial data using a sampling clock. A bit length counter determines a bit time by counting a number (m) of predetermined clock cycles, where the bit length terminal variably adjusts the number (m) of clock cycles of the bit length counter.