Adjustable Buffer Memory Space via Hierarchical L2P Mapping
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Solution Overview
Problem
Traditional memory sub-systems face challenges in efficiently managing buffer memory space, leading to suboptimal use of storage resources due to the large size of logical-to-physical memory address mapping data, which occupies significant space and limits the available buffer memory for host systems.
Innovation Solution
The solution involves reducing the amount of logical-to-physical memory address mapping data stored on the memory sub-system by changing its structure, implementing caching, and using thin provisioning of namespaces, thereby freeing up unused data storage space which can be allocated to increase the buffer memory space without requiring additional memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If logical-to-physical memory address mapping data is stored in traditional structure, then mapping functionality is maintained, but buffer memory space is insufficient
Solution Approach 1:
The mapping data structure is segmented into multiple levels (first level mapping data and second level mapping data), where the first level contains broader address ranges and the second level provides finer granularity. This segmentation reduces the amount of mapping data that must be held in buffer memory while maintaining complete mapping functionality.
Solution Approach 2:
The patent introduces a hierarchical dimension to the mapping structure, organizing mapping data across multiple levels rather than a single flat structure. This dimensional change allows buffer memory to store only essential first-level mapping data, while second-level data can be stored in slower, higher-capacity memory, thus expanding effective buffer space without losing mapping capability.
2Adaptability or versatility
If buffer memory space is increased to support more host systems, then storage flexibility improves, but mapping data storage capacity is reduced
Solution Approach 1:
By segmenting mapping data into hierarchical levels, the system can allocate buffer memory to store only the most frequently accessed first-level mapping data, while less frequently accessed second-level data is stored in alternative memory. This enables the system to support multiple host systems with flexible buffer allocation while maintaining complete mapping data storage capacity across the hierarchical structure.
Solution Approach 2:
The hierarchical mapping structure enables dynamic allocation of memory resources. Buffer memory can be dynamically configured to hold first-level mapping data structures, while second-level data structures are allocated in alternative memory, allowing the system to adapt buffer size and composition based on host system requirements without sacrificing total mapping data capacity.
3Adaptability or versatility
If multiple memory sub-system architectures are used to support different buffer sizes, then adaptability improves, but device complexity increases
Solution Approach 1:
The hierarchical mapping data structure serves as a universal solution that works across different buffer sizes and host system configurations. The same two-level structure can accommodate various buffer capacities by adjusting the granularity and scope of first-level versus second-level data, eliminating the need for multiple specialized architectures while maintaining adaptability to different use cases.
Data Source
AI summary
Various embodiments described herein provide for adjusting (e.g., increasing) buffer memory space, provided by memory (e.g., active memory) of a memory sub-system used to store logical-to-physical memory address (L2P) mapping data, by reducing the amount of L2P mapping data stored on the memory.