Adjustable High Resolution Dead Time PWM Signal Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current PWM power control systems face challenges in accurately inserting adjustable high-resolution dead time, especially in synchronous switch topologies, due to increasing switching frequencies and varying operating conditions, leading to inefficiencies and potential shootthrough faults.
Innovation Solution
A method and apparatus that utilize delaying circuitry and multiplexers to generate and select phases for shifting the rising and falling edges of PWM signals, allowing for high-resolution dead time insertion with software-calculated values, eliminating the need for on-the-fly counter decoding and enabling precise control of dead time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a time delay is set long enough to prevent shootthrough faults between complementary switches, then reliability is improved, but power loss increases due to extended dead time
Solution Approach 1:
The patent implements dynamic dead time adjustment by continuously monitoring current conditions, temperature, and load parameters, then automatically optimizing the dead time duration in real-time. This allows the system to use minimal dead time when conditions permit (reducing power loss) while ensuring sufficient dead time when safety requires it (preventing shootthrough), thereby resolving the contradiction between reliability and energy efficiency
Solution Approach 2:
The system changes the dead time parameter dynamically based on operating conditions. By adjusting this critical parameter according to real-time feedback from sensors and system state, the patent achieves both short dead time (for efficiency) and adequate shootthrough prevention (for reliability) under different operating scenarios
2Productivity
If dead time is adjusted with very fine granularity (sub nanosecond range) to match increasing switching frequencies, then productivity is improved, but device complexity increases due to requirements for picosecond-level counter decoding
Solution Approach 1:
The patent replaces complex digital counter decoding mechanisms with an analog delay line-based timing generation system. Instead of using digital counters that require picosecond-level decoding and processing, the invention uses analog delay elements that naturally provide the required sub-nanosecond resolution without complex digital logic, thereby achieving high switching frequency performance while significantly reducing device complexity
Solution Approach 2:
The patent introduces an analog delay line as an intermediary component between the control logic and the power switches. This intermediary provides precise time delay generation without requiring complex digital counter decoding, effectively mediating between the digital control domain and the analog power switching domain while simplifying the overall system architecture
3Loss of energy
If synchronous switch topologies are used to reduce power losses, then energy efficiency is improved, but device complexity increases due to requirements for dead time insertion control
Solution Approach 1:
The patent implements a self-adjusting dead time control mechanism that automatically adapts to system conditions without requiring complex external control. The control circuit monitors system state and autonomously adjusts dead time parameters, making the system self-regulating and reducing the need for complex external control logic while maintaining the efficiency benefits of synchronous topologies
Solution Approach 2:
The patent designs a control mechanism that serves multiple functions: it provides dead time insertion, monitors system conditions, adjusts timing parameters, and prevents shootthrough faults all within a single integrated control structure. This multi-functional approach reduces overall device complexity compared to having separate circuits for each function
Data Source
AI summary
The disclosure generally relates to a method and an apparatus for providing an adjustable high resolution dead time, and more specifically, to a method and an apparatus for inserting an adjustable high resolution dead time in a PWM signal. A method for inserting an adjustable high resolution dead time in a PWM signal includes receiving a clock signal at a delaying circuitry and generating, by the delaying circuitry, a plurality of phases, receiving the generated plurality of phases at a first multiplexer, and selecting and forwarding, by the first multiplexer, a first phase of the plurality of phases based on a first high resolution dead time value. The method further includes shifting a rising edge and/or a falling edge of the PWM signal using the received first phase forwarded by the first multiplexer.