Adjustable-Delay DPLL for Low-Noise Integer Clock Synchronization
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Solution Overview
Problem
In wireless networks, especially those operating at millimeter wave frequencies, phase noise caused by inconsistent delay elements in digital synchronization circuits leads to jitter and distorted signals, affecting throughput due to varying step sizes from process and temperature variance.
Innovation Solution
A digital phase-locked loop (DPLL) with cascaded delay elements is used to provide a quantized digital word equivalent to a time difference between the oscillator signal and the reference clock, with a method to select delay elements based on collective delay values to minimize phase noise by targeting subsections with finer resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay elements are used to synchronize clocks in digital synchronization circuits, then clock synchronization is achieved, but phase noise and jitter increase due to inconsistent step sizes from process and temperature variance
Solution Approach 1:
The delay line is divided into multiple delay elements with different delay characteristics. By segmenting the delay line and selecting specific elements based on measured delay values, the system achieves fine-grained phase adjustment while avoiding the inconsistent step sizes that cause jitter and phase noise
Solution Approach 2:
The system dynamically selects delay elements based on measured delay values and adjusts the phase by changing which delay element is activated. This parameter change approach allows the system to adapt to process and temperature variations, maintaining consistent phase accuracy without introducing jitter
2Device complexity
If delay elements with fixed step sizes are used, then device complexity is reduced, but manufacturing precision deteriorates due to process and temperature variance affecting delay consistency
Solution Approach 1:
The system performs preliminary measurement of delay values for each delay element during initialization or calibration. These measured values are stored and used to select the appropriate delay element during operation, compensating for manufacturing variations before the actual synchronization task begins
Solution Approach 2:
The system uses feedback from measured delay values to dynamically select which delay element to use. This feedback mechanism allows the system to compensate for process and temperature variations, maintaining consistent delay characteristics without requiring complex manufacturing precision
3Device complexity
If integer operation mode is used in DPLL, then device complexity is reduced, but phase noise increases due to quantization errors from coarse delay steps
Solution Approach 1:
The delay line is segmented into multiple elements with progressively finer delay steps. By using multiple segments with different resolutions, the system achieves fine phase adjustment capability while maintaining the simplicity of integer operation mode in the DPLL
Solution Approach 2:
The system transitions from a single-dimensional integer-based delay adjustment to a multi-dimensional approach by selecting from multiple delay elements with different delay characteristics. This dimensional change enables fine phase resolution without increasing DPLL operational complexity
Data Source
AI summary
Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry configured to, in a first mode, identify a delay element of a plurality of delay elements based on an associated delay value, and set an initial phase difference value to a phase difference value associated with the identified delay element. The processor circuitry may be further configured to, in a second mode, in a second mode, initialize the DPLL using the initial phase difference value, determine a phase error between a reference clock and a feedback clock based on the initial phase difference value, adjust an output clock signal based on the phase error.