Adjustable Delay Propagation for Page Buffer Driver Groups
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Solution Overview
Problem
Conventional 3D NAND Flash memory devices face challenges in managing peak power consumption during page buffer operations, which can exceed power specifications and availability, especially when large quantities of page buffer circuits are operated concurrently.
Innovation Solution
The implementation of a microelectronic device structure with a timing delay and page buffer driver section that staggers the control and operation of different groups of page buffers in time, using a timing delay chain and page buffer drivers to distribute power demand over a longer timeframe, thereby reducing peak power requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If large quantities of page buffer circuits are operated concurrently to increase memory density and performance, then productivity and memory capacity are improved, but peak power consumption exceeds power specifications and availability
Solution Approach 1:
The page buffer circuits are divided into multiple groups, with each group controlled by a separate page buffer driver. The drivers are distributed across the device and control different portions of page buffer circuits, allowing concurrent operation of multiple groups while limiting peak power consumption in any single region.
Solution Approach 2:
Page buffer drivers are activated in a staggered, periodic manner rather than all simultaneously. Each driver operates during specific time intervals, creating a distributed temporal pattern of activation that spreads peak power demands across different time periods while maintaining overall high productivity.
2Productivity
If all page buffer drivers are activated simultaneously to maximize data throughput, then productivity is improved, but power consumption spikes exceed available power supply
Solution Approach 1:
Page buffer drivers are activated in a staggered, periodic manner rather than all simultaneously. Each driver operates during specific time intervals, creating a distributed temporal pattern of activation that spreads peak power demands across different time periods while maintaining overall high productivity.
Solution Approach 2:
The system dynamically adjusts the activation timing of different page buffer drivers based on operational requirements. Drivers can be selectively enabled or disabled, and their activation times can be modified to optimize both power consumption and data throughput for different operating conditions.
3Productivity
If page buffer operations are concentrated in a single time window to improve efficiency, then productivity is improved, but power consumption exceeds power availability
Solution Approach 1:
The page buffer circuits are divided into multiple groups, with each group controlled by a separate page buffer driver. The drivers are distributed across the device and control different portions of page buffer circuits, allowing concurrent operation of multiple groups while limiting peak power consumption in any single region.
Solution Approach 2:
Page buffer drivers are activated in a staggered, periodic manner rather than all simultaneously. Each driver operates during specific time intervals, creating a distributed temporal pattern of activation that spreads peak power demands across different time periods while maintaining overall high productivity.
Data Source
AI summary
A microelectronic device comprises a microelectronic device structure comprising a section comprising page buffers, and an additional section horizontally neighboring the section and comprising page buffer drivers and a timing delay chain coupled to the page buffer drivers. Each of the page buffer drivers is coupled to different group of the page buffers than each other of the page buffer drivers. The timing delay chain comprises timing delay circuits coupled in series with one another. Each of the timing delay circuits is configured to adjustably delay propagation of a control signal therethrough. Memory devices, methods of operating memory devices, and electronic systems are also described.