Adjustable DLL Delay Chain for Clock Skew Synchronization
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Solution Overview
Problem
Internal delays in digital circuits cause clock skew, leading to unsynchronization of components and potential device malfunction or failure, which existing methods like PLL and DLL struggle to fully address due to limitations in fixed delay elements and jitter magnification.
Innovation Solution
A Delay-Locked Loop (DLL) system with an adjustable initial minimum number of delay elements, allowing for incremental delay adjustment to synchronize components by matching the delayed reference signal with the original, and enabling flexible configuration of the initial delay value to accommodate different applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed delay elements are used in DLL to correct clock skew, then synchronization is achieved, but jitter magnification occurs and limits adjustment flexibility
Solution Approach 1:
The patent applies dynamics by making the delay element adjustable rather than fixed. The delay amount can be dynamically changed based on the measured skew between reference and delayed signals, allowing the system to adapt to different conditions and minimize jitter magnification while maintaining synchronization.
Solution Approach 2:
The patent changes the delay parameter from a fixed value to an adjustable value. By allowing the delay amount to be modified based on actual signal characteristics and skew measurements, the system can optimize performance and reduce harmful jitter effects while maintaining reliable synchronization.
2Reliability
If delay elements are added to correct clock skew, then component synchronization improves, but device complexity increases
Solution Approach 1:
The patent applies self-service by enabling the delay element to automatically adjust its own delay amount based on feedback from skew detection. The system monitors the phase difference between reference and delayed signals and autonomously modifies the delay parameter to achieve and maintain synchronization, reducing the need for external intervention and simplifying overall system complexity.
Solution Approach 2:
The patent implements feedback by continuously monitoring the phase relationship between the reference signal and the delayed signal, then using this information to adjust the delay element parameters. This closed-loop control mechanism automatically maintains synchronization without requiring complex external configuration or intervention.
3Adaptability or versatility
If adjustable delay elements are implemented, then flexibility and jitter reduction improve, but initial configuration complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-configuring an initial minimum delay value before the device enters operation. This initial setting provides a reasonable starting point that simplifies the subsequent automatic adjustment process, allowing the system to quickly converge to the optimal delay value without requiring complex manual configuration or extensive calibration procedures.
Data Source
AI summary
Embodiment of the present invention relate to a method for receiving a first signal, determining a first characteristic of the first signal, the characteristic being a time based characteristic, receiving a second signal and processing the second signal through a predetermined range of delay elements, an initial minimum number of delay elements in the predetermined range being adjustable, the processed second signal having a second characteristic substantially corresponding to the first characteristic of the first signal.