Adjustable-Gain Phase Detection for Jitter-Tolerant Clock Recovery
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Solution Overview
Problem
Conventional phase detecting circuits in clock and data recovery systems face challenges in adjusting the gain curve to increase input jitter tolerance, especially at high frequencies, leading to increased noise, higher costs, and signal delay due to the use of high-frequency circuits and nonlinear bang-bang phase detectors.
Innovation Solution
A phase detecting circuit with multiple phase detectors and a logic circuit that compares a data signal to clock signals of the same frequency but different phases, generating control signals to adjust the gain curve through various logic operations, allowing the circuit to operate at a lower frequency and reduce the number of high-frequency components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a bang-bang phase detector is used in high-speed clock and data recovery circuits, then the circuit can operate at ultra-high frequencies, but the gain curve becomes fixed and cannot be adjusted to increase input jitter tolerance
Solution Approach 1:
The phase detector is divided into multiple parallel phase detection paths, each with its own D flip-flops and XOR gates. These parallel paths allow the circuit to process multiple phase comparisons simultaneously, enabling both high-frequency operation and adjustable gain characteristics through selective combination of path outputs.
Solution Approach 2:
The invention introduces dynamic control signals that can selectively enable or disable different phase detection paths based on the desired gain curve configuration. This dynamic switching capability allows the fixed bang-bang detector structure to achieve variable gain characteristics without compromising its high-frequency operation.
2Productivity
If high-frequency circuits are used to process data signals, then the data transmission speed is improved, but circuit noise and costs increase
Solution Approach 1:
The circuit uses periodic clock signals with different phases to sample the data signal at multiple points within each data signal period. This periodic sampling approach allows high-speed data transmission to be processed through lower-frequency clock operations, reducing high-frequency noise while maintaining transmission speed capability.
3Reliability
If extra circuits including counters or accumulators are added to compensate control signals, then input jitter tolerance is increased, but signal delay and extra jitter are generated
Solution Approach 1:
The circuit performs preliminary phase comparison and control signal generation in parallel paths before the main processing stage. By pre-computing multiple phase difference possibilities simultaneously, the circuit eliminates the need for sequential counter or accumulator operations that would introduce delay, while still achieving enhanced jitter tolerance through the combined results.
Data Source
AI summary
A phase detecting circuit having an adjustable gain curve includes a plurality of phase detectors and a logic circuit. The phase detectors detect phase differences between a data signal and a plurality of clock signals by comparison to output a plurality of control signals. The clock signals have the same frequency but different phases, and the frequency of the data signal is a multiple of the frequency of the clock signals. The logic circuit performs various logic operations according to these control signals to output at least one set of gain control signals for adjusting a gain curve of the phase detecting circuit.