Adjustable Gate-Length FET Structure Beyond Lithography Limits
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Solution Overview
Problem
Reducing the gate length of field effect transistors (FETs) to improve performance is limited by technology nodes and photolithographic resolution, hindering on-resistance reduction and switching speed enhancement.
Innovation Solution
A semiconductor structure with a primary and secondary gate structure configuration, including a patterned conformal dielectric layer, allows for adjustable effective gate length by biasing the secondary gate structures to reduce on-resistance and enhance switching speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the gate length of the FET is reduced to improve performance, then on-resistance decreases and switching speed increases, but the gate length reduction is limited by technology node and photolithographic resolution
Solution Approach 1:
The gate structure is divided into a primary gate and at least one secondary gate structure. The secondary gate structure is positioned adjacent to the primary gate and can be independently biased to control the effective gate length. This segmentation allows the effective gate length to be adjusted without changing the physical dimensions, thereby overcoming photolithographic resolution limits.
Solution Approach 2:
The effective gate length is made dynamically adjustable through independent biasing of the secondary gate structure relative to the primary gate. By applying different voltages to the secondary gate, the depletion regions can be extended or reduced, thereby dynamically changing the effective gate length between source and drain regions without physical modification.
2Reliability
If the gate length is reduced to reduce on-resistance, then performance improves, but further reduction is constrained by optical resolution limits
Solution Approach 1:
Instead of changing the physical gate length parameter which is constrained by photolithography, the invention changes the electrical parameter of effective gate length through voltage biasing. The secondary gate structure allows continuous adjustment of the effective gate length by modifying the depletion region extent, thereby achieving on-resistance reduction without hitting manufacturing precision limits.
3Productivity
If secondary gate structures are added to adjust effective gate length, then on-resistance reduces and switching speed increases, but device complexity increases
Solution Approach 1:
The secondary gate structure serves multiple functions: it controls the effective gate length, adjusts on-resistance, and can independently modulate switching characteristics. This multi-functionality justifies the added structural complexity by providing enhanced performance control that a single gate structure cannot achieve.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure effectively adjusts the gate length, reducing on-resistance and increasing switching speed through concurrent or selective biasing of secondary gate structures, thereby optimizing FET performance.
Implementation Method 1
biasing the at least one secondary gate structure reduces an effective gate length
Data Source
AI summary
Disclosed is a structure including a field effect transistor (FET). The FET includes, on an insulator layer above a substrate, source/drain regions and a section of a semiconductor layer extending laterally between the source/drain regions. A primary gate structure is made of the insulator layer and a well region in the substrate opposite at least the section of the semiconductor layer extending laterally between the source/drain regions. One or two secondary gate structures are on the semiconductor layer between and near one or both of the source/drain regions, respectively. The FET can further include a patterned conformal dielectric layer, which is on the center of the semiconductor layer between the source/drain regions, and which extends onto the secondary gate structure(s). Also disclosed are methods of operating the structure by biasing the secondary gate structure(s) to adjust the effective gate length of the FET and methods of forming the structure.