Adjustable Gate Resistance Transistor for High-Density Memory
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Solution Overview
Problem
Current electronic memory devices face challenges in increasing data storage capacity while maintaining or reducing size and cost, as well as improving performance, with traditional methods like reducing memory cell size leading to potential increases in bit cost due to rising process costs.
Innovation Solution
A memory device design featuring an array of memory cells with transistors and resistors, where the gate dielectric is switchable between different resistances to represent memory states, allowing for program, erase, and read operations through voltage applications, using materials like silicon dioxide, hafnium dioxide, and titanium dioxide, and incorporating a high-resistance layer between the gate dielectric and low-resistance layers to achieve bit density and cost efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced to increase bit density, then data storage capacity per unit area increases, but manufacturing process cost increases rapidly
Solution Approach 1:
The patent changes the electrical parameter (resistance) of the gate dielectric layer to create memory states, rather than relying solely on geometric scaling. By inducing soft breakdown to switch the gate dielectric between high and low resistance states, the invention achieves memory functionality without proportionally reducing memory cell dimensions, thereby avoiding the exponential increase in manufacturing costs associated with sub-10nm process scaling.
2Reliability
If traditional charge storage methods are used, then memory states are achieved through stored charge, but the device requires additional structures and higher power consumption
Solution Approach 1:
The patent extracts the charge storage function from the traditional transistor structure by utilizing the resistance change of the gate dielectric layer itself as the memory mechanism. This eliminates the need for separate charge storage structures such as floating gates or charge trapping layers, simplifying the device architecture and reducing power consumption while maintaining reliable memory state representation through high and low resistance states.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables increased bit density with lower power consumption and cost, utilizing soft breakdown conditions to change gate resistance, allowing for multi-level memory states and efficient data storage without the need for stored charge, thus overcoming the limitations of traditional approaches.
Implementation Method 1
The gate dielectric is switchable between first and second different resistances associated with respective first and second memory states. The first resistance of the gate dielectric can be associated with a soft breakdown (SBD) condition of the transistor.
Data Source
AI summary
A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in series with a resistance. The transistor includes a gate dielectric that is switchable between a plurality of different resistance values. The threshold voltage of the transistor changes according to the resistance value of the gate dielectric. Memory states of the memory cells can thus be associated with respective resistance values of the dielectric layer of the transistor.