Sense Amplifier Bias Circuit With Adjustable Load Widths
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Solution Overview
Problem
Current mode sense amplifiers in integrated circuits face challenges in maintaining a constant loop gain across variations in process, voltage, and temperature, especially in low voltage, low power systems, which affects their operating characteristics and sensitivity to differential input currents.
Innovation Solution
The implementation of a bias circuit and amplifier stage configuration that adjusts the loop gain by using transistors and resistances with specific scaling ratios and adjustable widths, along with a beta multiplier reference circuit, to maintain a substantially constant loop gain independent of process, voltage, and temperature variations, and allows for precharging of input/output nodes to a reference voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If diode coupled n-FET transistors are used to provide load, then loop gain remains substantially constant despite PVT variations, but supply voltage requirement increases
Solution Approach 1:
The patent changes the type of transistors used for the load from diode-coupled n-FETs to p-FETs, altering the electrical parameters of the circuit. This parameter change allows the load to be provided by p-FET transistors with adjustable widths, enabling loop gain control while reducing supply voltage requirements to only exceed the threshold voltage of the n-FET input transistors plus a voltage margin.
2Use of energy by moving object
If p-FET transistors are used to provide load, then supply voltage requirement decreases, but loop gain varies more with PVT variations
Solution Approach 1:
The patent implements a feedback mechanism where the widths of the p-FET load transistors are adjusted based on detected loop gain variations. By monitoring the loop gain and dynamically adjusting the p-FET widths, the system compensates for PVT variations and maintains substantially constant loop gain while operating at reduced supply voltages.
Solution Approach 2:
The patent introduces dynamic adjustability of the p-FET load transistor widths, transforming them from fixed-parameter components to dynamically controllable elements. This dynamic adjustment capability enables the circuit to adapt to PVT variations in real-time, maintaining loop gain stability while operating at lower supply voltages than conventional designs.
3Productivity
If loop gain is increased to greater than 1, then the circuit transitions to latch circuit behavior, but current sensing capability decreases
Solution Approach 1:
The patent employs dynamic control of the p-FET load transistor widths to adjust the loop gain according to operational requirements. By making the loop gain可调 (adjustable) rather than fixed, the circuit can switch between sensing mode (loop gain ≈ 1) and amplification mode (loop gain > 1) as needed, optimizing performance for different operational contexts.
Data Source
AI summary
Sense amplifiers including bias circuits are described. Examples include bias circuits having an adjustable width transistor. A loop gain of the bias circuit may be determined in part by the adjustable width of the transistor. Examples of sense amplifiers including amplifier stages configured to bias an input/output node to a reference voltage.