Adjustable Low-Pass Filter for Accurate PLL Lock Detection
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Solution Overview
Problem
Existing low pass filters in phase locked loops (PLL) and delay locked loops (DLL) fail to accurately determine locking states due to insufficient filtering of signals with varying pulse widths and high jitter, leading to erroneous operations and inability to perform operations after locking.
Innovation Solution
A low pass filter with adjustable bandwidth, comprising a driver unit, charge/discharge units, a comparator unit, and a switching unit, which adjusts its bandwidth based on a bandwidth expansion signal to effectively filter input pulses and generate a stable PLL locking signal, using resistive elements and capacitors to control RC delay time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fixed bandwidth low pass filter is used, then the circuit structure is simple, but the filter cannot accurately determine locking states when signals have varying pulse widths and high jitter
Solution Approach 1:
The low pass filter transitions from a fixed bandwidth design to a dynamic bandwidth design where the bandwidth expansion control signal (BW_CTRL) adjusts the filter bandwidth based on operating conditions. The switching unit selectively connects different RC circuits with different time constants (τ1, τ2, τ3, τ4) to the input node, allowing the filter to adapt its bandwidth dynamically. This resolves the contradiction by enabling accurate locking state detection under varying signal conditions while maintaining reasonable circuit complexity through controlled adaptability.
Solution Approach 2:
The filter bandwidth parameter is changed dynamically based on the bandwidth expansion control signal. When BW_CTRL is at a first logic level, the filter operates with a first bandwidth suitable for normal operation. When BW_CTRL switches to a second logic level, the filter bandwidth expands to handle signals with large pulse width variations and high jitter. This parameter change approach allows the same circuit to optimize performance for different operating scenarios, resolving the accuracy-complexity contradiction.
2Measurement precision
If the filter bandwidth is expanded to handle large pulse width variations, then the filtering accuracy for varying pulse widths improves, but the response time increases
Solution Approach 1:
The filter dynamically adjusts its bandwidth and response characteristics based on the bandwidth expansion control signal. During normal operation (first logic level), the filter maintains a narrower bandwidth with faster response for quick locking detection. When large pulse width variations occur (second logic level), the filter expands bandwidth and adjusts RC time constants to improve filtering accuracy. This dynamic adjustment resolves the contradiction between filtering accuracy and response speed by optimizing both parameters according to operating conditions.
Solution Approach 2:
The bandwidth expansion control signal operates periodically or event-driven, switching the filter between normal and expanded bandwidth modes. During normal locking operation, the filter uses standard RC time constants for rapid response. When pulse width variations exceed thresholds, the control signal triggers a mode switch to expanded bandwidth configuration with adjusted RC circuits, improving filtering accuracy temporarily. This periodic action resolves the speed-accuracy contradiction by applying different optimization strategies at different times.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The adjustable bandwidth low pass filter ensures accurate filtering of signals in both locking and unlocking states, even with significant frequency variations and jitter, preventing erroneous operations and enabling stable PLL locking signals.
Implementation Method 1
a capacitor C connected between the node NODE1 and the ground voltage terminal
Implementation Method 2
the supply voltage supplied to the node NODE1 is charged into the capacitor C
Implementation Method 3
a comparator using a Schmitt trigger S1 connected to the node NODE1
Data Source
AI summary
A low pass filter includes a driver unit configured to output a voltage proportional to an input pulse width, a charge/discharge unit configured to charge the output voltage of the driver unit, a comparator unit configured to compare an output voltage of the charge/discharge unit with a reference value to output a square wave signal, and a switching unit configured to switch the charge/discharge unit to an operation state, based on a bandwidth expansion signal.