Adjustable Power Limiter with Integrated Detector for Leakage Reduction
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Solution Overview
Problem
Existing adjustable power limiters in RF systems suffer from higher power leakage and less ideal limiting functions compared to fixed limiters, while also lacking adjustability and rapid response times, especially when integrated with other circuitry in semiconductor processes like bulk silicon, SOI, and SOS.
Innovation Solution
A self-activating, adjustable threshold power limiter is designed using a stack of field-effect transistors (FETs) with a common control voltage and an integrated power detector circuit, which adjusts the threshold power point by modulating the ON resistance of the FETs, reducing leakage and enhancing the limiting slope through voltage rectification and control voltage generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If adjustable limiters are used to permit systems to limit power at various levels, then adaptability is improved, but power leakage increases and limiting function becomes less ideal
Solution Approach 1:
The patent implements a feedback mechanism where a power detector monitors the input power level and automatically adjusts the gate voltage of the FETs accordingly. This closed-loop control enables the limiter to maintain ideal limiting performance across varying power levels while minimizing power leakage, resolving the contradiction between adaptability and energy loss.
Solution Approach 2:
The patent employs dynamically adjustable FET gate voltages controlled by the power detector output. Instead of fixed biasing, the gate voltages are continuously adjusted based on the detected power level, enabling the limiter to adapt its characteristics in real-time and achieve both adjustability and low power leakage simultaneously.
2Speed
If fixed limiters with back-to-back P-i-N diodes are used, then response time is improved and limiting function is near-ideal, but adjustability is lost and integration with standard semiconductor processes is difficult
Solution Approach 1:
The patent changes the operational parameters of the FETs by dynamically adjusting their gate voltages based on detected power levels. This parameter adjustment enables the FETs to function as adjustable limiters while maintaining fast response times comparable to fixed limiters, as the FETs operate in their saturation region where they exhibit rapid switching characteristics.
Solution Approach 2:
The patent substitutes the mechanical/P-i-N diode-based limiting mechanism with an electrically-controlled FET system. The FETs, controlled by voltage signals from the power detector, replace the fixed P-i-N diode structure, enabling both fast electrical response and programmable adjustability through voltage control.
3Ease of manufacture
If FETs are used in standard bulk silicon, SOI, and SOS processes, then ease of manufacture and integration are improved, but fast P-i-N diodes are not available and response time may be affected
Solution Approach 1:
The patent implements a self-service mechanism where the power detector automatically senses the input power level and adjusts the FET gate voltages without external intervention. This self-adjusting capability enables the FET-based limiter to achieve optimal performance in standard semiconductor processes, compensating for the absence of fast P-i-N diodes through intelligent voltage control.
Solution Approach 2:
The patent applies preliminary biasing to the FET gates through the power detector circuit, which pre-establishes appropriate operating voltages before the limiting action occurs. This preliminary voltage setup ensures that the FETs are primed for rapid response when power limiting is needed, compensating for the slower response characteristics of FETs compared to P-i-N diodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a more ideal limiting function with reduced power leakage, short response time, and adjustable threshold, making it suitable for high-power applications and easy integration with other circuitry, while improving linearity by managing accumulated charge.
Implementation Method 1
A power detector circuit is coupled between a node V1 on the signal line between the source and the receiver, and gate resistors of the FETs. The power detector circuit provides voltage rectification and control voltage generation
Data Source
AI summary
A limiter having a more ideal limiting function, a short response time, and an adjustable limiting threshold. In one embodiment, a self-activating limiter stack is coupled between circuit ground and a signal line between a source and a receiver. The limiter stack limits the power from the source when the voltage on the signal line exceeds the breakdown voltage of the limiter stack. The threshold of the limiter stack is controlled in part by a first control voltage applied to a control input. A rectifying power detector circuit connected between a node on the signal line and the control input of the limiter stack provides a second control voltage as a function of the signal power at the node. The combined first and second control voltages are applied to the control input to modulate the ON resistance of the limiter stack, thereby limiting the leakage power reaching the protected receiver.