Adjustable Programming Pulses for Multi-Level Cell Read Window Stability
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Solution Overview
Problem
Multi-level memory cells experience read errors due to reduced read windows caused by shifting voltage threshold distributions during cycling, leading to collapsed read windows and increased bit error rates.
Innovation Solution
Modifying the characteristics of programming pulses, such as magnitude, width, or time between pulses, based on reliability metrics like bit error rate and usage cycles, to reverse the movement of shifted threshold voltage distributions and increase read windows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level memory cells are programmed to store multiple states, then storage capacity is improved, but read window stability deteriorates due to shifting voltage threshold distributions
Solution Approach 1:
The patent applies dynamics by making the programming pulse characteristics adjustable rather than fixed. The system dynamically modifies pulse magnitude, width, or timing based on detected threshold voltage shifts and reliability metrics, allowing the programming process to adapt to changing cell states and maintain read window stability throughout the memory cell's lifecycle
Solution Approach 2:
The patent implements parameter changes by varying programming pulse characteristics (magnitude, width, timing) based on detected threshold voltage distributions. The system monitors reliability metrics and adjusts pulse parameters accordingly to reverse threshold shifts and maintain stable read windows, directly addressing the contradiction between multi-state storage and read stability
2Quantity of substance
If programming pulses are applied to write intermediate states, then storage density is improved, but bit error rate increases due to collapsed read windows
Solution Approach 1:
The patent implements feedback by monitoring threshold voltage distributions and reliability metrics after programming operations, then using this information to adjust subsequent programming pulse characteristics. This closed-loop approach detects read window collapse early and modifies programming parameters to reverse the effect, reducing bit error rates while maintaining high storage density
Solution Approach 2:
The system changes programming pulse parameters (magnitude, width, timing) based on detected threshold voltage shifts caused by intermediate state programming. By adjusting these parameters in response to observed effects, the system reverses threshold movements that cause read window collapse and reduces bit error rates
3Duration of action of stationary object
If memory cells are cycled through multiple states, then data retention is improved, but threshold voltage distributions shift causing read errors
Solution Approach 1:
The patent applies dynamics by continuously adapting programming pulse characteristics based on the memory cell's cycling history and observed threshold voltage shifts. The system modifies pulse parameters in real-time to counteract drift caused by repeated state transitions, maintaining read accuracy throughout the data retention period
Solution Approach 2:
The patent implements preliminary anti-action by detecting early signs of threshold voltage shift during cycling and applying compensatory programming pulses before read errors occur. The system proactively reverses threshold movements by adjusting pulse characteristics, preventing read window collapse rather than reacting to errors after they occur
Data Source
AI summary
Methods, systems, and devices for adjustable programming pulses for a multi-level cell are described. A memory device may modify a characteristic of a programming pulse for an intermediate logic state based on a metric of reliability of associated memory cells. The modified characteristic may increase a read window and reverse a movement of a shifted threshold voltage distribution (e.g., by moving the threshold voltage distribution farther from one or more other voltage distributions). The metric of reliability may be determined by performing test writes may be a quantity of cycles of use for the memory cells, a bit error rate, and/or a quantity of reads of the first state. The information associated with the modified second pulse may be stored in fuses or memory cells, or may be implemented by a memory device controller or circuitry of the memory device.