Adjustable Quantization Circuit for Multi-Range ADC Threshold Control

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Solution Overview

Problem

Analog-to-digital converters (ADCs) face challenges in accommodating different communications standards due to varying signal ranges, leading to inadequate performance and increased size and noise in existing systems, which attempt to adjust analog input signals using variable gain amplifiers and attenuators.

Innovation Solution

A quantization circuit with a comparator array and variable resistance elements that adjust threshold voltages to change the voltage resolution and range, allowing a single ADC to support multiple operating modes by converting analog signals to thermometer code and adjusting effective resistance to suit different signal standards.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If variable gain amplifiers and attenuators are added to adjust analog input signals, then the ADC can accommodate different signal ranges, but the device size and current requirements increase

Engineering Contradiction:
Improvesignal range accommodationVSAvoidcomponent count
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a single ADC architecture that can operate across multiple signal ranges (e.g., 1Vpp and 0.5Vpp) by integrating variable resistance elements directly into the quantization circuit. This eliminates the need for separate ADCs or additional external components for each signal standard, achieving multi-functionality within a unified device structure.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines the signal adjustment function with the quantization circuit by integrating variable resistance elements (such as switched resistor networks) directly into the ADC architecture. This merging of functions allows the ADC to adapt to different signal ranges without requiring separate variable gain amplifiers or attenuators, thereby reducing overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

2Adaptability or versatility

If variable gain amplifiers and attenuators are added to adjust analog input signals, then the ADC can accommodate different signal ranges, but the noise performance deteriorates

Engineering Contradiction:
Improvesignal range accommodationVSAvoidnoise
Core Design Contradiction:
Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

The patent extracts the signal level adjustment function from external components (variable gain amplifiers and attenuators) and implements it directly within the quantization circuit through variable resistance elements. This extraction eliminates the need for intermediate signal conditioning stages that would introduce additional noise, allowing direct conversion of the input signal across different ranges.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces variable resistance elements as intermediary components within the quantization circuit that enable smooth transition between different signal ranges. These resistance elements act as mediators that adjust the effective input range without requiring aggressive amplification or attenuation stages, thereby minimizing noise introduction while maintaining signal integrity.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If a single ADC is designed for a particular communications standard, then the voltage resolution is optimized for that standard, but the ADC cannot accommodate other standards with different signal ranges

Engineering Contradiction:
Improvevoltage resolutionVSAvoidcommunications standard compatibility
Core Design Contradiction:
Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic adjustability within the quantization circuit by incorporating variable resistance elements that can be controlled through digital signals. This allows the ADC to dynamically change its voltage resolution and input range characteristics to match different communications standards (e.g., WCDMA, LTE, GSM) without requiring physical reconfiguration or multiple dedicated ADCs.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the electrical parameters (resistance values, threshold voltages) of the quantization circuit components based on the detected communications standard. By adjusting these parameters through variable resistance elements and controlled voltage dividers, the ADC maintains optimized voltage resolution for each standard while accommodating different signal ranges, thus achieving both precision and versatility.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables efficient conversion across various signal standards with reduced noise and component complexity, allowing a single ADC to operate effectively across multiple communications standards without the need for separate ADCs or additional components.

Implementation Method 1

A variable resistance element is coupled to the voltage divider arrangement, wherein the control node and the variable resistance element are cooperatively configured to adjust the threshold voltage for at least one comparator of the comparator array by adjusting the effective resistance of the variable resistance element in response to the control signal

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS7852253B2Digitally adjustable quantization circuit
Publication Date: 2010.12.14 NXP USA INC
  • US7852253B2 patent drawing
  • US7852253B2 patent drawing
  • US7852253B2 patent drawing

AI summary

Apparatus and methods are provided for converting an analog input signal to a digital output value. A quantization circuit comprises an input node and a comparator array, wherein each comparator of the comparator array is coupled to the input node. A voltage divider arrangement is coupled to the comparator array and configured to establish a respective threshold voltage for each comparator of the comparator array. The comparator array generates a digital code based on the input signal and the respective threshold voltage for each comparator. A control node is coupled to the voltage divider arrangement, wherein the control node and the voltage divider arrangement are cooperatively configured to adjust the threshold voltage for at least one comparator of the comparator array in response to a control signal at the control node.