Adjustable Resistance Bit Line Architecture for Leakage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory devices face challenges with increased leakage currents through unselected memory cells due to process, voltage, and temperature variations, which affect memory array efficiency and reliability.
Innovation Solution
The implementation of an adjustable resistance bit line structure that can be set into a high resistance or non-conducting state by applying a voltage to the select gate, reducing leakage currents through unselected memory cells by making unselected vertical bit lines highly resistive or non-conductive, while maintaining low resistance for selected bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If process geometries are shrunk to reduce cost per bit, then memory capacity increases, but leakage currents through unselected memory cells increase
Solution Approach 1:
The patent applies local quality by creating distinct resistance states in different regions of the bit line structure. The selective gate controls specific segments of the bit line to have high resistance when unselected, while selected segments maintain low resistance. This localized resistance modulation eliminates leakage currents in unselected memory cells while preserving signal transmission in selected cells, directly resolving the contradiction between increased memory capacity and reduced leakage currents.
Solution Approach 2:
The patent implements dynamics by making the bit line resistance adjustable and controllable through the selective gate. The resistance state of bit line segments is dynamically changed based on selection signals - unselected segments are switched to high resistance state to block leakage, while selected segments remain in low resistance state for signal transmission. This dynamic resistance control allows the system to adapt to different operational states and eliminate the harmful leakage effect.
2Reliability
If adjustable resistance bit line structure is implemented to reduce leakage currents, then memory reliability improves, but device complexity increases
Solution Approach 1:
The patent merges the bit line and gate structures into an integrated selective bit line architecture. The selective gate is formed as part of the bit line structure itself, sharing common fabrication processes and material layers. This merging reduces the need for separate complex control circuits and additional fabrication steps, thereby improving memory reliability through better integration while minimizing the increase in device complexity.
Solution Approach 2:
The selective gate structure serves multiple functions: it acts as both a selection mechanism and a resistance control element. The same gate structure that selects memory cells for operation also modulates the resistance of bit line segments, eliminating the need for separate resistance control circuits. This multi-functionality reduces overall device complexity while achieving the reliability improvement through leakage current reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces leakage currents, improving memory array efficiency, enabling larger memory array sizes, reducing power consumption, and enhancing memory reliability by minimizing voltage requirements during operations.
Implementation Method 1
The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate (SG) portion of the bit line structure
Data Source
AI summary
Systems and methods for reducing leakage currents through unselected memory cells of a memory array including setting an adjustable resistance bit line structure connected to the unselected memory cells into a high resistance state or a non-conducting state during a memory operation are described. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is electrically isolated from the intrinsic polysilicon portion (e.g., via an oxide layer between the intrinsic polysilicon portion and the select gate portion). The memory cells may comprise a first conductive metal oxide (e.g., titanium oxide) that abuts a second conductive metal oxide (e.g., aluminum oxide) that abuts a layer of amorphous silicon.