Adjustable Resistor With Thin Insulator For Code Hiding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing integrated circuit technologies using floating-gate memories struggle to effectively hide a code, as modifications in resistor dimensions or dopant concentrations can be easily detected, making it difficult to securely store and conceal information.
Innovation Solution
The development of adjustable resistors formed on a substrate with a first polysilicon layer covered by a thin insulating layer and a second polysilicon layer, where the resistance value can be adjusted by applying a voltage through a conductive via, allowing for the creation of resistors that can hide a code without additional manufacturing steps, using a stack of silicon oxide and nitride layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If resistor dimensions or dopant concentrations are modified to store a code, then the code can be stored in the integrated circuit, but the code can be easily detected through reverse engineering
Solution Approach 1:
The patent changes the physical state of the insulator layer from thick (non-conductive) to thin (leaky/conductive) to adjust the resistor value. This parameter change in insulator thickness enables code storage while maintaining detectability resistance, as the thin insulator region is difficult to distinguish from the surrounding structure without specialized analysis.
Solution Approach 2:
The patent introduces local variations in insulator layer thickness, creating specific regions with thin insulators that provide leakage paths. These localized thin regions are distributed throughout the resistor structure, enabling code encoding while maintaining overall structural uniformity that resists detection.
2Adaptability or versatility
If a thin insulator layer is introduced to adjust resistance, then the resistance value can be varied, but additional manufacturing steps are required
Solution Approach 1:
The patent performs preliminary etching of the insulator layer to create thin regions before depositing the second polysilicon layer. This preliminary action prepares the structure for subsequent resistance adjustment through voltage application, enabling resistance variation without requiring additional processing steps after the basic resistor formation.
Solution Approach 2:
The patent merges the code storage function with the resistance adjustment function by using the same thin insulator regions for both purposes. The leakage paths through thin insulators serve dual roles: encoding the code and providing the mechanism for resistance adjustment, thereby eliminating the need for separate structures.
3Reliability
If the insulator layer thickness is reduced to create leakage paths, then the resistance can be adjusted, but the structural integrity may be compromised
Solution Approach 1:
The patent applies local quality by creating thin insulator regions only in specific areas where leakage paths are needed, while maintaining thick insulator layers in other regions for structural support and electrical isolation. This localized thinning approach balances the need for resistance adjustment with maintaining overall structural integrity.
Solution Approach 2:
The patent provides beforehand cushioning by maintaining thick insulator regions surrounding the thin insulator areas. These thick regions act as cushioning elements that prevent complete structural failure while allowing the thin regions to provide the necessary leakage paths for resistance adjustment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for the secure hiding of a code in integrated circuits by varying the resistance of the polysilicon layer, making it difficult to detect, and maintains resistance variation across a wide temperature range, ensuring the code's integrity and security.
Implementation Method 1
a first polysilicon layer covered with a second insulating layer of a first thickness, except in a region where the first polysilicon layer is covered with a thin insulator layer of a second thickness smaller than the first thickness
Implementation Method 2
First and fourth regions 5 and 31 of the layer of the first polysilicon level are N-type doped, for example, with a dopant element concentration approximately ranging from 5.1018 to 5.1019 atoms/cm3
Data Source
AI summary
An adjustable resistor formed on a first insulating layer of a substrate, including: a first polysilicon layer covered with a second insulating layer of a first thickness, except in a region where the first polysilicon layer is covered with a thin insulator layer of a second thickness smaller than the first thickness; a second polysilicon layer covering the second insulating layer and the thin insulator layer; on each side of the second insulating layer and at a distance from it, a first and a second conductive vias providing access to the terminals of the resistor on the first polysilicon layer; and a third conductive via providing access to a contacting area on the second polysilicon layer.