Adjustable High Voltage Start-Up Circuit for Power Management

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Solution Overview

Problem

Traditional high voltage start-up circuits have fixed and unadjustable power-on start-up and restart times, leading to a contradiction where optimizing one time period compromises the other, resulting in inefficient power consumption and application performance.

Innovation Solution

A high voltage start-up circuit with adjustable start-up time, utilizing a combination of NMOS transistors, diodes, resistors, comparators, and counters to regulate the power-on and restart times by generating control signals that adjust the threshold voltages and edge counting, allowing flexible configuration of start-up and restart processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the power-on start-up speed is increased to meet application requirements, then the start-up time is reduced, but the restart power consumption increases due to larger input power during restart

Engineering Contradiction:
Improvepower-on start-up speedVSAvoidrestart power consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamics by making the start-up circuit configurable between two distinct modes: a first configuration for power-on start-up with higher speed, and a second configuration for restart operations with lower power consumption. This is achieved through control logic that selectively activates different circuit paths based on whether the system is undergoing initial power-on or restart, allowing optimal performance characteristics for each scenario rather than being constrained by a fixed design

Inventive Principle:
Principle #15Dynamics

2Use of energy by moving object

If the restart speed is reduced to decrease power consumption during restart, then the power consumption is reduced, but the power-on start-up speed is also reduced and may not meet application requirements

Engineering Contradiction:
Improverestart power consumptionVSAvoidpower-on start-up speed
Core Design Contradiction:
Use of energy by moving objectVSSpeed

Solution Approach 1:

The patent segments the start-up circuit into distinct functional paths: one dedicated to power-on start-up operations and another for restart operations. By dividing the circuit functionality and using separate control paths, the system can optimize each segment for its specific purpose - the power-on path prioritizes speed while the restart path prioritizes power efficiency, eliminating the need to compromise either parameter

Inventive Principle:
Principle #1Segmentation

3Device complexity

If the power-on start-up time and restart time are made identical in traditional start-up mode, then the circuit design is simplified, but the power consumption and performance cannot be optimized for different operational scenarios

Engineering Contradiction:
Improvecircuit design complexityVSAvoidapplication-specific optimization
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent implements multi-functionality by creating a unified start-up circuit that can perform two different operational modes: power-on start-up and restart. The circuit includes configurable elements that allow it to adapt its behavior based on the operational context, providing both speed-optimized and power-efficient configurations within a single integrated design, thus achieving versatility without requiring separate dedicated circuits

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9431892B1High voltage start-up circuit with adjustable start-up time
Publication Date: 2016.08.30 SUZHOU POWERON IC DESIGN
  • US9431892B1 patent drawing
  • US9431892B1 patent drawing
  • US9431892B1 patent drawing

AI summary

A high voltage start-up circuit with adjustable start-up time, wherein, the drain electrode of the first NMOS transistor is connected with a first terminal of the first resistor, a gate electrode of the second NMOS transistor and a negative terminal of the diode; a source electrode of the first NMOS transistor, together with a positive terminal of the diode, is connected to the power ground; a drain electrode of the second NMOS transistor, together with a second terminal of the first resistor, is connected with a port SW of a chip; a source electrode of the second NMOS transistor, together with a first terminal of the second resistor, is connected with a power port VDD of the chip. The circuit can adjust the start-up time and the restart time of the chip flexibly.