Adjusted Read Signal for Partially Programmed Memory Blocks

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Solution Overview

Problem

As memory devices are scaled to smaller sizes, the available read window between different programmed states shrinks, leading to potential read errors, which existing read retry mechanisms and error recovery methods attempt to address but at the cost of reduced performance in terms of latency.

Innovation Solution

The implementation of an adjusted read signal level based on the proximity of the physical address to the last written page in a partially programmed block, which is determined simultaneously with the logical-to-physical address translation, allowing for accurate data retrieval without the need for additional system access or flag reading.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory devices are scaled to smaller sizes, then integration density is improved, but read window between different programmed states shrinks causing read errors

Engineering Contradiction:
Improveintegration densityVSAvoidread window
Core Design Contradiction:
Quantity of substanceVSMeasurement precision

Solution Approach 1:

The patent changes the read signal level parameter dynamically based on the programming status of the block. When a block is partially programmed, a first read signal level is used; when fully programmed, a second read signal level is used. This parameter adjustment compensates for the shrinking read window in scaled memory devices, maintaining measurement precision despite reduced integration density margins.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If read retry mechanisms and error recovery are employed, then read accuracy is improved, but latency increases reducing performance

Engineering Contradiction:
Improveread accuracyVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary action by determining the programming status of the block before executing the read operation. By checking whether the block is partially or fully programmed in advance, the system can select the appropriate read signal level beforehand, ensuring read accuracy without requiring read retry mechanisms, thus avoiding additional latency.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If read signal level is adjusted based on programming status, then read accuracy in partially programmed blocks is improved, but system complexity increases

Engineering Contradiction:
Improveread accuracyVSAvoidcontrol logic
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The memory system serves itself by using its own programming status information to determine the appropriate read signal level. The controller monitors the programming status of blocks and automatically adjusts the read signal level without requiring external intervention or complex additional control logic, maintaining simplicity while improving read accuracy.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS9236133B2Adjusted read for partially programmed block
Publication Date: 2016.01.12 MICRON TECHNOLOGY INC
  • US9236133B2 patent drawing
  • US9236133B2 patent drawing
  • US9236133B2 patent drawing

AI summary

The present disclosure is related to an adjusted read for a partially programmed block. A number of methods can include receiving a read request including a logical address, translating the logical address to a physical address and simultaneously determining whether a physical address associated with the read request is in a block that is partially programmed, and in response to the physical address being in the block that is partially programmed, adjusting a read signal level based on a proximity of the physical address to a last written page in the block.