Adjustment Circuit for Partitioned Memory Blocks
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Solution Overview
Problem
Memory systems face challenges in optimizing memory density and read performance due to variations in access frequency and voltage exposure between code and data memory sectors, leading to stress breakdown and reduced cycling endurance in data memory and insufficient read windows across temperature variations.
Innovation Solution
The memory system incorporates partitioned memory blocks with an adjustment circuit that dynamically adjusts verify reference currents based on temperature and memory type, and a driver circuit with a 'boost' function to reduce wordline voltage settling time, optimizing storage capacity and read performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If memory blocks are partitioned into code and data memory sectors with different verify reference currents, then cycling endurance of data memory is improved, but device complexity increases
Solution Approach 1:
The memory block is divided into two distinct sectors: code memory sector and data memory sector. Each sector has its own verify reference current (first verify reference current for code memory, second verify reference current for data memory). This segmentation allows different verification conditions to be applied to different memory types, extending the cycling endurance of data memory by using a more conservative verify reference current that causes less stress breakdown.
Solution Approach 2:
Different verify reference currents are applied to different memory sectors based on their specific requirements. The code memory sector uses a first verify reference current optimized for code storage, while the data memory sector uses a second verify reference current optimized for data storage and frequent cycling. This local differentiation allows each sector to operate under optimal conditions for its intended use.
2Device complexity
If a single verify reference current is used for all memory blocks, then device complexity is reduced, but read performance across temperature variations deteriorates
Solution Approach 1:
The verify reference current is made dynamic rather than static. The adjustment circuit dynamically selects between the first verify reference current and the second verify reference current based on the memory type (code or data) being verified. This dynamic adaptation allows the system to maintain optimal read performance across different memory sectors and temperature variations without requiring a single fixed current value that would compromise reliability.
3Reliability
If verify reference current is increased to improve read window, then read performance is improved, but stress breakdown in data memory increases
Solution Approach 1:
Different verify reference currents are applied to different memory sectors based on their specific requirements. The code memory sector uses a first verify reference current optimized for code storage, while the data memory sector uses a second verify reference current optimized for data storage and frequent cycling. This local differentiation allows each sector to operate under optimal conditions for its intended use.
Solution Approach 2:
The verify reference current parameter is changed based on memory type. By adjusting the verify reference current value according to whether the memory sector stores code or data, the system optimizes the read window for each sector while controlling stress breakdown. Data memory uses a verify reference current that provides sufficient read window while minimizing stress on the memory cells during verification operations.
Data Source
AI summary
The present disclosure describes an adjustment circuit that can be used, for example, in a memory system with partitioned memory blocks. The adjustment circuit can include a controller circuit, a timer circuit, and a temperature adaptive reference (TAR) generator. The controller circuit can be configured to output a control signal that indicates a memory type (e.g., code memory or data memory) associated with a partitioned memory block. The timer circuit can be configured to output a timing signal for a read memory operation based on the control signal. And, the TAR generator can be configured to adjust a verify reference current for a verify memory operation based on temperature, where the verify reference current is set based on the control signal.