ADLL Built-In Self-Test for Precise Delay Offset Verification
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Solution Overview
Problem
ADLL circuits in integrated circuits, such as memory devices, face challenges in testing and verifying the hardware path due to coarse measurement granularity of external testers, making it difficult to ensure correct delay settings and detect failures effectively.
Innovation Solution
A Built-In Self-Test (BIST) circuit is integrated into the IC to program ADLL circuits with multiple delay settings, measuring actual time offsets between delayed clock signals and generating test results, using a Digital Ring Oscillator to count pulse widths indicative of these offsets, thus verifying correct delay application with minimal additional on-chip hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external testers are used to test ADLL circuits, then testing can be performed externally, but measurement precision is insufficient due to coarse measurement granularity
Solution Approach 1:
A BIST circuit is introduced as an intermediary component between the ADLL circuit and the external tester. This BIST circuit includes a delay measurement unit that precisely measures delay values by counting clock cycles, and a comparison unit that compares measured delays with expected values. The BIST circuit translates the fine-grained delay measurements into testable signals for external testers, thereby achieving precise measurement without requiring the external tester itself to have fine measurement capability.
2Measurement precision
If BIST circuit is integrated into IC to achieve precise measurement, then measurement precision is improved, but device complexity increases due to additional on-chip hardware
Solution Approach 1:
The BIST circuit is designed to perform multiple functions: it generates test patterns, measures delay values, compares measurements with expected values, and generates test results. By consolidating these functions into a single integrated circuit block, the patent reduces overall device complexity compared to having separate dedicated circuits for each function. The delay measurement unit uses the existing clock signal from the ADLL circuit itself, rather than requiring external reference clocks, further reducing hardware requirements.
3Reliability
If multiple delay settings are tested to cover failure modes, then reliability of testing is improved, but loss of time increases due to extensive testing
Solution Approach 1:
The comparison unit implements a staged testing approach where it first performs a quick coarse comparison to identify obviously failing test cases, and only performs detailed fine-grained comparison for test cases that pass the coarse check. This partial action strategy ensures that most failing cases are detected quickly without undergoing the full time-consuming measurement and comparison sequence, thereby maintaining high reliability while reducing average test time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The BIST circuit effectively detects failures and deviations in ADLL circuit performance across various delay settings, covering a range of failure modes while being insensitive to PVT variations, ensuring accurate testing with minimal hardware overhead.
Implementation Method 1
The test circuit includes a Digital Ring Oscillator (DRO) that is configured to count the actual time offset. In an embodiment, the test circuit is configured to derive, from the first and second delayed versions of the input clock signal, a pulse having a width that is indicative of the actual time offset, and to trigger the DRO with the pulse.
Data Source
AI summary
An electronic circuit includes an adaptive delay circuit and a test circuit. The adaptive delay circuit is configured to receive an input clock signal, to further receive a delay setting that specifies first and second delays, and to generate first and second delayed versions of the input clock signal that are delayed relative to the input clock signal by the first and second delays, respectively. The test circuit is configured to test the adaptive delay circuit by (i) programming the adaptive delay circuit with multiple different delay settings that each specifies a respective first delay and a respective second delay, (ii) for each of the multiple delay settings, measuring an actual time offset between the first and second delayed versions of the input clock signal, and (iii) generating a test result based on actual time offsets measured for the multiple different delay settings.