ADPLL Phase Tracking Using ADC Sampling Instead of TDCs

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional all-digital phase locked loops (ADPLLs) employing time-to-digital converters (TDCs) suffer from poor integral non-linearity (INL) and differential non-linearity (DNL) performance, as well as high noise and power consumption, making them less ideal for phase detection.

Innovation Solution

Utilizing a pair of analog-to-digital converters (ADCs) to sample the phase difference between an output signal and a reference signal in the ADPLL, improving INL, DNL, and power consumption performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a time-to-digital converter (TDC) is employed as a phase detector in an ADPLL, then the phase detection function is achieved, but the integral non-linearity (INL) and differential non-linearity (DNL) performance deteriorates

Engineering Contradiction:

Improvephase detection accuracyVSAvoidintegral non-linearity and differential non-linearity

Core Design Contradiction:

Measurement precisionVSManufacturing precision

Solution Approach 1:

The patent replaces the conventional TDC (time-to-digital converter) with an ADC (analog-to-digital converter) for phase detection. This substitution changes the measurement approach from time-based to amplitude-based sampling, thereby improving INL and DNL performance while maintaining phase detection functionality.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Measurement precision

If a time-to-digital converter (TDC) is employed as a phase detector in an ADPLL, then the phase detection function is achieved, but the noise performance deteriorates

Engineering Contradiction:

Improvephase detection accuracyVSAvoidnoise

Core Design Contradiction:

Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent replaces the TDC with an ADC-based sampling system that captures the phase difference signal in the amplitude domain. This substitution reduces the introduction of quantization noise and jitter that are inherent in time-based conversion methods, thereby improving overall noise performance.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Measurement precision

If a time-to-digital converter (TDC) is employed as a phase detector in an ADPLL, then the phase detection function is achieved, but the power consumption increases

Engineering Contradiction:

Improvephase detection accuracyVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent substitutes the power-hungry TDC circuitry with an ADC-based sampling approach. The ADC consumes less power while providing equivalent or superior phase detection accuracy, thereby reducing the overall power consumption of the ADPLL system.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

4Device complexity

If conventional TDCs are used in an ADPLL, then the device structure is maintained, but the performance with respect to INL, DNL, and power consumption deteriorates

Engineering Contradiction:

Improvedevice structureVSAvoidintegral non-linearity and differential non-linearity

Core Design Contradiction:

Device complexityVSManufacturing precision

Solution Approach 1:

The patent replaces the conventional TDC structure with an ADC-based phase detection system. This substitution maintains the overall ADPLL device structure while significantly improving INL and DNL performance through amplitude-based sampling instead of time-based conversion.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20260031824A1All-digital phase locked loop phase tracking techniques

Publication Date: 2026.01.29 MARVELL ASIA PTE LTD

AI summary

An ADPLL circuit includes a phase comparator for comparing a phase of a reference clock (REFCLK) input signal with a phase of a digitally controlled oscillator clock (DCO_CLK) signal output from a DCO. The phase comparator includes a first ADC connected to receive a REF_P signal corresponding to the phase of the REFCLK signal via a first switch and output an ADC0 signal and a second ADC connected to receive the signal REF_P via a second switch and output an ADC1 signal. The ADPLL circuit further includes a digital filter for receiving the ADC0 and ADC1 signals and determining therefrom a difference between the phases of the DCO_CLK signal and the REFCLK signal. The digital filter provides a DCO control signal to the DCO to control a frequency of operation of the DCO based on the phase difference.