ADPLL Bandwidth Shifting Without Lock Loss or Large Memory
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Solution Overview
Problem
Existing all-digital phase locked loop (ADPLL) systems face challenges in changing loop bandwidth without disturbing the lock, which can affect ongoing wireless communications.
Innovation Solution
The implementation of a digital loop filter with flip-flops to store output values, allowing for continuous amplification changes and preventing bandwidth switching from causing the ADPLL to lose its lock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the loop bandwidth is increased at the start of lock, then the locking speed is improved, but the phase noise outside the channel bandwidth increases
Solution Approach 1:
The patent implements dynamic bandwidth switching by changing the loop bandwidth from a first bandwidth during acquisition to a second bandwidth during tracking. The digital loop filter adjusts its bandwidth based on the lock status, using a wider bandwidth initially to speed up locking, then narrowing it to reduce phase noise once locked.
2Productivity
If the loop bandwidth is switched to change loop gain, then the locking performance is improved, but the lock operation is disturbed
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing compensation values in lookup tables before bandwidth switching occurs. When the loop bandwidth changes, the corresponding compensation value is immediately applied to the proportional path, anticipating the disturbance and counteracting it before it affects the lock operation.
Solution Approach 2:
The patent implements feedback by using the output of the digital loop filter from a previous time instance and feeding it back to the proportional path. This feedback mechanism compensates for disturbances caused by bandwidth switching, maintaining lock stability during transitions between different bandwidth states.
3Adaptability or versatility
If unlimited bandwidth switching is implemented, then the adaptability is improved, but the device complexity increases
Solution Approach 1:
The patent changes the parameter representation by using logarithmic indexing for the lookup tables. Instead of storing full amplification parameters, it stores compact index values that map to pre-calculated compensation values. This parameter transformation enables unlimited bandwidth switching while keeping the memory footprint manageable through efficient data representation.
Data Source
AI summary
This disclosure is directed towards systems and methods that improve bandwidth shifting operations of an ADPLL without losing a lock of the ADPLL and having the benefit of being able to change the bandwidth an unlimited amount of times. Indeed, a processor may transmit amplification parameters to the ADPLL to implement a bandwidth shift. The shift may occur in response to a enable signal, such as a gear trigger control signal (gear_retime signal) or a enable signal generated to cause alignment of the shifting with a clock signal (e.g., enable signal generated by AND logic gates). These systems and methods described herein many enable multiple bandwidth changing operations to occur without compromising the complexity and footprint of the system.