ADPLL Calibration Circuit for DCO Phase Noise Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
All-digital phase-locked loops (ADPLLs) face performance limitations due to phase noise in digitally controlled oscillators (DCOs), requiring an optimization method that improves circuit architecture without introducing side effects.
Innovation Solution
An ADPLL circuit with a calibration method that includes a phase detector and a calibration circuit to modify the current of a DCO's current source based on phase error values, optimizing the bias current to minimize phase noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If a DCO circuit is used in an ADPLL, then the ADPLL can be fully digitalized and integrated, but phase noise performance deteriorates
Solution Approach 1:
The patent applies preliminary action by performing calibration operations before normal ADPLL operation. The calibration circuit pre-adjusts the DCO current sources based on phase error measurements taken during a calibration phase, so that when normal operation begins, the DCO is already optimized for minimal phase noise. This resolves the contradiction by preparing the system in advance to overcome the inherent phase noise issues of digital oscillators.
Solution Approach 2:
The patent changes physical parameters of the DCO circuit by dynamically adjusting current source levels through calibration. The calibration circuit modifies bias currents in the DCO based on measured phase error, thereby changing the operating parameters of the digital oscillator to optimize phase noise performance. This allows the fully digital ADPLL to achieve better phase noise characteristics without sacrificing integration benefits.
2Reliability
If calibration circuit is added to optimize phase noise, then phase noise performance improves, but device complexity increases
Solution Approach 1:
The calibration circuit is designed to perform multiple functions: it measures phase error, determines optimal current settings, and adjusts DCO parameters. By making the calibration circuit multi-functional, the patent reduces the need for separate dedicated circuits for each function, thereby limiting the increase in device complexity while still achieving phase noise optimization.
Solution Approach 2:
The calibration circuit uses the existing phase detector within the ADPLL to generate phase error measurements for calibration purposes. Rather than requiring a completely separate measurement system, the circuit repurposes existing components to serve the calibration function, thereby minimizing additional complexity while improving phase noise performance.
Data Source
AI summary
An all-digital phase-locked loop (ADPLL) circuit and a calibration method thereof are provided. The ADPLL circuit includes a digitally controlled oscillator (DCO) circuit, a phase detector circuit, and a calibration circuit coupled between the DCO circuit and the phase detector circuit. The DCO circuit generates a clock signal according to a frequency control signal. The phase detector circuit generates a phase error value according to a reference signal and the clock signal. More particularly, after the ADPLL circuit performs a locking operation for a period of time, the frequency control signal is tied at a locked value which is obtained when the ADPLL circuit performs the locking operation, and the calibration circuit may modify a current of at least one current source within the DCO circuit according to the phase error value.