ADPLL Clock Synchronization for Multi-Clock Digital Sampling
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Solution Overview
Problem
Existing solutions for synchronizing data from devices operating at distinct clock frequencies with a central device using a global clock are either complex, power-consuming, or not applicable to all devices.
Innovation Solution
A synchronizing digital device incorporating a local oscillator, an all-digital phase-locked loop (ADPLL), digital signal generating circuitry, sampling circuitry, and an interface, which generates a sampling control signal to synchronize digital signals with a bus clock frequency, using a phase-error detector, digital filter, and sigma-delta modulator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-frequency master clock signal is sent to all slave devices to replace local oscillator signals, then synchronization robustness is improved, but power consumption increases and device complexity increases
Solution Approach 1:
The patent introduces an all-digital phase-locked loop (ADPLL) as an intermediary device that receives the master clock signal and generates a synthesized clock signal. This ADPLL acts as a mediator between the master clock and the slave device operations, allowing the slave device to use a locally generated clock signal that is synchronized to the master clock, thereby avoiding the need to distribute high-frequency clock signals to all slave devices while maintaining synchronization robustness
Solution Approach 2:
The patent replaces the traditional approach of distributing high-frequency clock signals through physical wiring with a digital signal processing approach using ADPLL. Instead of mechanically/electrically distributing the master clock signal to all slave devices, the system uses digital phase detection, filtering, and signal generation to synthesize synchronized clock signals locally at each slave device, reducing power consumption and wiring complexity
2Reliability
If resampling is carried out within slave devices using slow bus signals, then circuit complexity increases, but synchronization is achieved
Solution Approach 1:
The patent replaces complex analog resampling circuits with an all-digital phase-locked loop (ADPLL) implementation. The ADPLL uses digital phase detection, digital filtering, and digital signal generation to achieve frequency synthesis and synchronization. This digital approach simplifies the circuit architecture compared to traditional analog resampling methods while maintaining synchronization accuracy
Solution Approach 2:
The patent changes the operating parameters of the synchronization system by using an all-digital approach operating at lower frequencies. The ADPLL processes phase error signals and generates control signals at frequencies suitable for digital logic operation, avoiding the need for high-frequency analog circuits. This parameter change from high-frequency analog to low-frequency digital operation reduces circuit complexity while achieving the same synchronization function
3Reliability
If resampling operations are performed to synchronize data, then synchronization is achieved, but noise is introduced that degrades the signal
Solution Approach 1:
The patent replaces analog resampling operations that introduce noise with an all-digital phase-locked loop (ADPLL) system. The digital nature of the ADPLL components (phase detector, filter, signal generator) eliminates analog noise sources such as clock jitter and thermal noise that plague analog resampling circuits. The digital system processes signals in the digital domain where noise can be more effectively managed and filtered
Solution Approach 2:
The ADPLL acts as an intermediary that cleanly transfers synchronization information from the master clock to the slave device without introducing significant noise. The digital phase detector and digital filter in the ADPLL provide clean, noise-free signal processing that mediates between the master clock signal and the slave device operations, avoiding the noise degradation associated with analog resampling
Data Source
AI summary
A device includes a local oscillator, an all-digital phase-locked loop, a digital signal generator, sampling circuitry, and an interface. The local oscillator generates a local clock signal. The all-digital phase locked loop generates a sampling control signal. The ADPLL includes a phase-error detector, a digital filter and a sigma-delta modulator. The phase detector generates a phase error signal based on a loop clock signal and a received reference signal. The digital filter generates a signal indicative of a frequency ratio between a frequency of the reference clock signal and the local clock frequency based on the phase error signal. The sigma-delta modulator generates a modulated signal based on the signal indicative of the frequency ratio. The sampling control signal is based on the modulated signal. The sampling circuitry samples digital signals generated by the digital signal generator at a sampling frequency, which is a function of the sampling control signal.