ADPLL Clock Synchronization Using Two-Flop and PFD Control
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Solution Overview
Problem
In frequency divider based All Digital Phase-Locked Loops (ADPLLs), clock synchronization between a reference clock and a divider clock can introduce metastability and increase noise due to asynchronous operation during the phase locking stage.
Innovation Solution
A clock synchronization unit incorporating a two-flop synchronizer, phase frequency detector (PFD), and synchronization control circuit is used to perform clock synchronization between the reference clock and divided clock, replacing the synchronization process with PFD operation, which generates charge pump control signals to adjust current sources in the charge pump unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a one-flop synchronizer is used for clock synchronization, then the device complexity is reduced, but metastability occurs during phase tracking stage
Solution Approach 1:
The synchronizer is divided into two separate flip-flops operating in sequence. The first flip-flop samples the reference clock with the divided clock, and the second flip-flop samples the output of the first flip-flop. This segmentation allows the synchronization process to occur in two stages, reducing the probability of metastability while maintaining a relatively simple overall structure.
2Device complexity
If a one-flop synchronizer is used for clock synchronization, then the device complexity is reduced, but noise increases
Solution Approach 1:
By segmenting the synchronization into two flip-flop stages, each stage contributes to noise reduction. The first flip-flop reduces the immediate noise impact, and the second flip-flop further filters residual noise, achieving cumulative noise reduction without significantly increasing device complexity.
3Reliability
If PFD operation is used to replace clock synchronization, then metastability is reduced, but the device complexity increases
Solution Approach 1:
The PFD operation is merged with the clock synchronization process. The PFD outputs are directly used to control the two-flop synchronizer, combining the phase detection function with the synchronization function in a unified structure. This integration reduces the need for separate control logic and minimizes overall device complexity.
Solution Approach 2:
The synchronization unit is designed to perform multiple functions: phase detection, frequency detection, and clock synchronization. By making the unit universal, the patent eliminates the need for separate dedicated circuits for each function, thereby reducing overall device complexity while maintaining high reliability through PFD operation.
4Device complexity
If traditional clock synchronization is used, then the synchronization process is simple, but in-band noise floor increases
Solution Approach 1:
The traditional single-stage synchronization is segmented into two flip-flop stages, each contributing to noise filtering. This segmentation maintains a relatively simple synchronization process while achieving superior noise performance through the cumulative effect of two sampling stages.
Data Source
AI summary
Embodiments of a clock synchronization unit of an All Digital Phase-Locked Loop (ADPLL), a successive approximation register (SAR) Time-to-Digital Converter (TDC) of an ADPLL and a method for clock synchronization in an ADPLL are disclosed. In one embodiment, a clock synchronization unit of an ADPLL includes a two-flop synchronizer, a phase frequency detector (PFD) connected to the two-flop synchronizer, and a synchronization control circuit configured to control the two-flop synchronizer and the PFD to perform clock synchronization between a reference clock input signal and a divided clock input signal and to control the two-flop synchronizer and the PFD to replace a performance of the clock synchronization between the reference clock input signal and the divided clock input signal with a PFD operation. Other embodiments are also described.