ADPLL Coarse-Fine Tuning for PVT-Stable Frequency Control

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Solution Overview

Problem

All-digital phase-locked loops (ADPLLs) face challenges in reducing circuitry and power consumption due to a high covering range ratio, which is exacerbated by process, voltage, and temperature (PVT) variations, leading to increased complexity and energy usage.

Innovation Solution

The ADPLL is designed with a coarse-tuning and fine-tuning stage, where the fine-tuning stage's covering range is dynamically controlled to decrease the overall covering range ratio by dynamically adjusting the code of coarse-tuning, using a combination of circuits and logic gates to manage voltage ranges and adjust frequencies accordingly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the covering range ratio is increased to handle PVT variations, then the frequency accuracy and adaptability are improved, but the circuitry complexity and power consumption increase

Engineering Contradiction:
Improveadaptability to PVT variationsVSAvoidcircuitry complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The frequency tuning range is segmented into two distinct stages: a coarse-tuning stage that covers a wide frequency range with low resolution, and a fine-tuning stage that covers a narrow frequency range with high resolution. This segmentation allows the system to achieve high adaptability across the full range without requiring the fine-tuning circuitry to handle the entire range, thereby reducing overall circuitry complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically switches between coarse-tuning and fine-tuning modes based on the current operating conditions and PVT variations. The coarse-tuning stage is activated when large frequency adjustments are needed, while the fine-tuning stage is activated for precise frequency adjustments. This dynamic operation optimizes the covering range ratio adaptively without permanently increasing circuitry complexity.

Inventive Principle:
Principle #15Dynamics

2Adaptability or versatility

If the covering range ratio is increased to handle PVT variations, then the frequency accuracy and adaptability are improved, but the power consumption increases

Engineering Contradiction:
Improveadaptability to PVT variationsVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

By segmenting the tuning range into coarse and fine stages, the system activates only the necessary tuning stage for each operating condition. The coarse-tuning stage consumes less power for large adjustments, while the fine-tuning stage consumes more power only when high precision is required. This segmentation prevents continuous high power consumption across the entire frequency range.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system applies partial action by using only the necessary portion of the tuning range for each adjustment. Instead of continuously engaging the full fine-tuning range, the system uses coarse-tuning for the majority of frequency adjustments and resorts to fine-tuning only when precise frequency control is needed, thereby reducing overall power consumption.

Inventive Principle:
Principle #16Partial or excessive action

3Device complexity

If the number of bits for fine-tuning code is reduced to decrease circuitry, then the circuitry complexity is reduced, but the frequency precision is degraded

Engineering Contradiction:
ImprovecircuitryVSAvoidfrequency precision
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The frequency tuning precision is segmented between two stages: the coarse-tuning stage provides low-resolution frequency adjustment with fewer bits, and the fine-tuning stage provides high-resolution frequency adjustment with more bits. The combined precision of both stages achieves the required overall frequency precision while using fewer total bits than a single-stage fine-tuning system would require.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system transitions from a single-dimensional fine-tuning approach to a two-dimensional approach combining coarse-tuning and fine-tuning stages. Each stage operates in its own dimensional space with appropriate bit resolution, allowing the system to achieve high overall precision without requiring excessive bits in a single dimension.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

4Adaptability or versatility

If the coarse-tuning stage is used to cover a wide frequency range, then the covering range is improved, but the frequency precision is degraded

Engineering Contradiction:
Improvefrequency range coverageVSAvoidfrequency precision
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The frequency tuning function is segmented into two specialized stages: the coarse-tuning stage is optimized for wide frequency range coverage with lower precision, while the fine-tuning stage is optimized for high frequency precision with a narrower range. This segmentation allows each stage to be optimized for its specific function rather than compromising either range or precision in a single stage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The coarse-tuning stage and fine-tuning stage are merged into a unified frequency control system where their outputs are combined. The coarse-tuning provides the base frequency with wide range coverage, and the fine-tuning adds precise adjustments on top of that base. The combination of both stages achieves both wide frequency range coverage and high frequency precision simultaneously.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9379718B2All-digital phase-locked loop (ADPLL)
Publication Date: 2016.06.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9379718B2 patent drawing
  • US9379718B2 patent drawing
  • US9379718B2 patent drawing

AI summary

An all-digital phase-locked loop (ADPLL) is provided. The ADPLL comprises a first circuit and a second circuit. The first circuit is configured to monitor a first signal and set a voltage of a second signal to a voltage within a first voltage range when a code of fine-tuning is equal to a first specified value. The first circuit is configured to set a voltage of a third signal to a voltage within a second voltage range when the code of fine-tuning is equal to a second specified value. The second circuit is configured to increase a code of coarse-tuning when the voltage of the second signal is within the first voltage range, and decrease the code of coarse-tuning when the voltage of the third signal is within the second voltage range. The ADPLL provides a target frequency despite changes in at least one of process, voltage or temperature.