ADPLL Frequency Generator With LMS DCO Gain Calibration
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Solution Overview
Problem
Conventional analog phase-locked loops (PLLs) are prone to errors and require complex recalibration during frequency hopping, leading to inefficiencies in digital radio systems, while existing digital PLL (DPLL) and all-digital PLL (ADPLL) solutions do not adequately address the need for precise gain calibration of digitally controlled oscillators (DCOs) in wireless communication standards.
Innovation Solution
The implementation of a Least Mean Squares (LMS)-based calibration unit within an ADPLL system that iteratively calibrates the DCO gain during frequency hopping, using a filtered phase error to generate an estimated DCO normalization value, allowing for accurate two-point direct modulation and reduced locking time across channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional analog PLL is used, then the system can operate with simple structure, but it is prone to errors and requires complex recalibration during frequency hopping
Solution Approach 1:
The patent replaces the conventional analog PLL with an all-digital PLL (ADPLL) system, substituting analog components with digital equivalents. Specifically, the voltage-controlled oscillator (VCO) is replaced with a digitally-controlled oscillator (DCO), and the phase detector is replaced with a time-to-digital converter (TDC). This digital substitution eliminates analog errors while maintaining system functionality, directly resolving the contradiction between structural simplicity and reliability.
2Ease of manufacture
If conventional analog PLL is used, then the initial design is simpler, but it requires complex recalibration during frequency hopping
Solution Approach 1:
The patent implements a calibration unit that performs preliminary calibration of the DCO gain at the beginning of frequency hopping operations. By pre-calibrating the DCO using a least mean squares (LMS) algorithm based on phase error measurements, the system eliminates the need for complex recalibration during each frequency hop. This preliminary action stores calibration data that can be reused, significantly reducing subsequent recalibration complexity.
3Area of stationary object
If DCO is used in ADPLL, then area is reduced and process migration is enabled, but precise gain calibration is not adequately addressed
Solution Approach 1:
The patent implements a feedback-based calibration mechanism where the calibration unit continuously monitors phase error between the reference clock and oscillator clock during frequency hopping. Using this feedback information, the system applies the LMS algorithm to iteratively adjust and calibrate the DCO gain, achieving precise calibration without requiring additional hardware area or complex external equipment.
Data Source
AI summary
A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) Obtained according to the estimated DCO normalization value. An associated method is also disclosed.