ADPLL DCO Gain Normalization with Split-Precision Multipliers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Prior art gain normalization circuits in ADPLL-based transmitters require high precision multipliers on critical paths, leading to latency and high current consumption, and are prone to unwanted perturbations when dynamic changes are made to frequency gain.
Innovation Solution
The proposed solution splits gain normalization multiplication functionality between a modulating path with full bit resolution high precision multiplication and a PLL loop with significantly lower resolution multiplication, reducing complexity and allowing dynamic changes without perturbing the system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high precision multiplier is used in the PLL loop for gain normalization, then the modulation accuracy is improved, but the latency and current consumption increase significantly
Solution Approach 1:
The patent segments the gain normalization function into two separate multipliers: one for the modulation path and one for the PLL loop. The modulation path multiplier handles full bit resolution multiplication for accurate modulation, while the PLL loop multiplier uses reduced precision (e.g., 3-bit or 4-bit) since it only needs to maintain loop stability. This segmentation allows the critical modulation path to maintain high accuracy without forcing the PLL loop to use equally complex multiplication logic, thereby reducing overall latency.
Solution Approach 2:
The patent applies different precision levels to different parts of the system based on their specific requirements. The modulation path receives full precision treatment where accuracy is critical, while the PLL loop receives reduced precision treatment where only stability is required. This local differentiation of quality allows the system to achieve high modulation accuracy without incurring the full latency penalty of high-precision multiplication throughout the entire loop.
2Measurement precision
If a high precision multiplier is used in the PLL loop for gain normalization, then the modulation accuracy is improved, but the current consumption increases
Solution Approach 1:
The patent segments the gain normalization function into two separate multipliers: one for the modulation path and one for the PLL loop. The modulation path multiplier handles full bit resolution multiplication for accurate modulation, while the PLL loop multiplier uses reduced precision (e.g., 3-bit or 4-bit) since it only needs to maintain loop stability. This segmentation allows the critical modulation path to maintain high accuracy without forcing the PLL loop to use equally complex multiplication logic, thereby reducing overall power consumption.
Solution Approach 2:
The patent applies different precision levels to different parts of the system based on their specific requirements. The modulation path receives full precision treatment where accuracy is critical, while the PLL loop receives reduced precision treatment where only stability is required. This local differentiation of quality allows the system to achieve high modulation accuracy without incurring the full power consumption penalty of high-precision multiplication throughout the entire loop.
3Adaptability or versatility
If dynamic changes are made to the frequency gain in the PLL loop, then the system adaptability is improved, but unwanted perturbations are introduced to the loop output
Solution Approach 1:
The patent segments the gain control into two independent paths: the modulation path multiplier and the PLL loop multiplier. Dynamic changes to frequency gain can be applied to the modulation path without necessarily affecting the PLL loop multiplier, or vice versa. This segmentation isolates the sources of gain adjustment, allowing dynamic adaptability in the modulation path while maintaining stability in the PLL loop by using simplified control logic for the loop multiplier.
Solution Approach 2:
The patent introduces separate gain control mechanisms for the two paths, acting as intermediaries that decouple the dynamic gain adjustment from the PLL loop stability requirements. The modulation path multiplier can respond dynamically to frequency gain changes while the PLL loop multiplier maintains stable, simplified control, preventing direct transmission of perturbations to the loop output.
Data Source
AI summary
A novel mechanism for gain normalization of a digitally controlled oscillator (DCO) in an all digital phase locked loop (ADPLL)-based transmitter that is operative to split the gain normalization multiplication functionality between a modulating path and a PLL loop. The gain normalization of the modulation loop (referred to as modulation path multiplier) comprises a full bit resolution high precision multiplication function. The gain normalization of the PLL loop, on the other hand, is of significantly lower resolution, hence much lower complexity multiplier logic circuitry is required.