ADPLL Dither Compensation for TDC Quantization Noise
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Solution Overview
Problem
All-digital phase locked loops (ADPLLs) suffer from significant in-band spurious tones due to the finite resolution of time-to-digital converters (TDCs), which degrade the accuracy of phase information and introduce quantization noise, worsened by analog mismatches and non-linearities.
Innovation Solution
Introducing a dither signal to corrupt the digital word generated by the TDC, either by delaying the reference clock or oscillating signal, and using a pseudo-random dither signal with adjustable gain to randomize quantization errors and counteract non-linearities, minimizing in-band noise through a look-up table and digital feed-forward compensation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a time-to-digital converter (TDC) with finite resolution is used in an all-digital phase locked loop, then the ADPLL can be implemented with digital components and minimal analog blocks, but quantization noise is introduced that degrades phase information accuracy
Solution Approach 1:
The patent combines multiple TDC readings with different resolutions (integer counter and fractional counter) to create a composite measurement that achieves higher effective resolution than either component alone. This composite approach allows the system to maintain digital implementation simplicity while improving phase measurement accuracy beyond what a single finite-resolution TDC could provide.
2Measurement precision
If the TDC resolution is increased to reduce quantization noise, then phase measurement accuracy improves, but the device complexity and hardware resources increase
Solution Approach 1:
The patent segments the TDC measurement function into two separate counters: an integer counter that handles coarse phase measurements and a fractional counter that handles fine phase measurements. This segmentation allows each counter to be optimized for its specific resolution requirement, achieving high overall measurement precision without requiring a single overly complex high-resolution TDC.
3Measurement precision
If a fractional counter is used to improve TDC resolution, then quantization noise is reduced, but the device complexity increases due to additional hardware components
Solution Approach 1:
The patent merges the integer counter and fractional counter outputs through a weighted combination process, where the fractional counter output is scaled and added to the integer counter output. This merging strategy integrates the fine-resolution fractional measurements with the coarse integer measurements to produce a high-precision phase measurement without requiring separate independent processing paths, thereby reducing overall system complexity.
4Measurement precision
If analog calibration methods are used to correct TDC non-linearities, then measurement accuracy improves, but the complexity of the calibration system increases
Solution Approach 1:
The patent replaces analog calibration mechanisms with a fully digital calibration approach. Instead of using analog components to correct TDC non-linearities, the invention uses digital lookup tables and computational algorithms to measure and compensate for non-linearities in the integer and fractional counters. This substitution of digital for analog calibration reduces hardware complexity while maintaining or improving measurement accuracy.
Data Source
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AI summary
A method of improving noise characteristics of an all-digital phase locked loop generating a feedback word representing a continuous-time oscillating signal, including a time-to-digital converter input with the continuous-time oscillating signal and a reference signal function of a reference clock, the time-to-digital converter generating a digital word representing either the ratio between the oscillating signal and the reference signal or the DCO output phase, the feedback word being a function of said digital word, comprises the step of corrupting with a dither signal at least one among the reference clock, the digital word and the oscillating signal. This method is implemented by a respective feedback circuit for an all-digital phase locked loop.