ADPLL Dithered TDC Feedback for Spurious Tone Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
All-digital phase locked loops (ADPLLs) suffer from in-band spurious tones due to the finite reapproach of the time-to-digital converter (TDC), which degrades the accuracy of phase information and introduces quantization noise, worsened by analog mismatches and non-linearities.
Innovation Solution
A dither signal is added to the digital word generated by the TDC, either to the reference clock or the oscillating signal, with a variable delay element and a properly shaped dither signal to randomize quantization errors and counteract non-linearities, using a pseudo-random sequence and look-up table for compensation to minimize in-band noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a time-to-digital converter (TDC) is used to replace divider, PFD and CP in an ADPLL, then the ADPLL achieves wide programmability and easy technology scaling, but the finite reapproach of the TDC introduces quantization noise and spurious tones that degrade phase information accuracy
Solution Approach 1:
A dither signal is introduced as an intermediary element between the TDC output and the feedback path. This dither signal acts as a mediator that randomizes the quantization errors produced by the TDC's finite reapproach, converting deterministic spurious tones into randomized noise that can be filtered more effectively, thereby improving phase information accuracy while maintaining the TDC-based architecture
Solution Approach 2:
The system changes the temporal parameters of the signals by introducing a variable delay element that applies different delay values to the dither signal based on lookup table entries. This parameter change allows the dither signal to be synchronized and adjusted to optimally counteract the quantization noise at different operating conditions, improving measurement precision without sacrificing adaptability
2Measurement precision
If a fractional counter is used to improve TDC reapproach, then the ADPLL performance is significantly improved, but the system complexity increases due to the need for additional fractional counting logic
Solution Approach 1:
The invention extracts the fractional counting function from the traditional counter architecture and implements it through a dither signal addition approach. Instead of using a complex fractional counter that requires additional logic circuits, the system adds a dither signal to the integer counter output, which effectively achieves fractional resolution without the complexity of dedicated fractional counting hardware
3Object-generated harmful factors
If dither signal is added to randomize quantization errors, then spurious tones are reduced, but the in-band noise may increase due to the added signal
Solution Approach 1:
The system employs periodic dither signal sequences with specific periods that are chosen to push the dither-induced noise energy out of the critical in-band region. By carefully selecting the dither signal period and using variable delay to adjust timing, the system achieves spurious tone reduction while minimizing in-band noise contamination through periodic modulation techniques
Data Source
AI summary
An all-digital phase locked loop (ADPLL) generates a feedback word representing a continuous-time oscillating signal. The ADPLL includes a time-to-digital converter (TDC) configured to be input with the continuous-time oscillating signal and a reference signal. The reference signal is a function of a reference clock signal. The TDC is configured to generate a digital word, the feedback word being a function of the digital word. The ADPLL includes a delay circuit configured to be input with at least one of the reference clock signal and the continuous-time oscillating signal and to be controlled by a first dither signal.