All-Digital PLL Edge Prediction for Fast Low-Power Phase Locking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices, such as high-speed DRAMs, face challenges in providing high-frequency clock signals required for phase locked loops, existing solutions like DLLs struggle with fast phase locking due to the difficulty in generating high-frequency external clock signals, and ADPLLs face challenges in simultaneous phase and frequency detection without an oscillator.
Innovation Solution
An all-digital phase locked loop (ADPLL) is designed to reduce the number of counters and time-to-digital converters by predicting edge position information and selecting output clocks, allowing for efficient processing of integer and fraction part phase information using a single counter and two TDCs, respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an ADPLL uses an oscillator to generate high-frequency output clock signals, then the frequency multiplication capability is improved, but the device complexity and power consumption increase due to simultaneous phase and frequency detection requirements
Solution Approach 1:
The patent removes the oscillator from the ADPLL structure, extracting only the necessary frequency multiplication function. By using a DCO that can be controlled by digital signals and a phase detector that compares the DCO output with a divided version of itself, the system achieves frequency multiplication without requiring simultaneous phase and frequency detection, thereby reducing circuit complexity.
Solution Approach 2:
The patent replaces the traditional analog oscillator-based frequency multiplication with a digitally-controlled approach. The DCO is controlled by a frequency control word (FCW) that determines the output frequency, and the phase detector uses digital logic to compare phases, substituting analog components with digital ones to reduce complexity.
2Speed
If an ADPLL simultaneously detects phase and frequency using an oscillator, then frequency multiplication is achieved, but the power consumption increases
Solution Approach 1:
The patent removes the oscillator component that consumes significant power for simultaneous phase and frequency detection. By using a DCO controlled by digital frequency information and a phase detector that operates with reduced functionality (comparing DCO output with divided DCO output), the system achieves frequency multiplication with lower power consumption.
Solution Approach 2:
The patent discards the continuous simultaneous phase and frequency detection function of traditional oscillators and recovers the essential frequency multiplication capability through a different mechanism - using the DCO's digital control input and a phase detector that operates at a reduced rate, thereby recovering the frequency multiplication function with lower power consumption.
3Speed
If a DLL is used for fast phase locking, then the phase generation speed is improved, but the adaptability to high-frequency operations deteriorates due to external clock signal limitations
Solution Approach 1:
The patent introduces an intermediary approach where the phase detector compares the DCO output with a divided version of the same DCO output rather than with an external high-frequency clock. This intermediary comparison method allows the system to achieve fast phase locking while being adaptable to high-frequency operations without requiring external high-frequency clock signals.
Solution Approach 2:
The patent changes the operating parameters by using a frequency control word (FCW) to digitally control the DCO output frequency. This allows the system to adapt to different high-frequency operations by changing the FCW parameter rather than requiring external high-frequency clock signals, thereby improving adaptability while maintaining fast phase locking capability.
Data Source
AI summary
An all digital phase locked loop (ADPLL) includes an integer part phase processing circuit that outputs an integer part frequency signal using a first value and a second value. The first value is obtained by counting edges of one of a plurality of output clock signals. The second value indicates current edge position information on an edge position of an external reference clock signal with respect to the plurality of output clock signals. The ADPLL further includes a fraction part phase processing circuit that selects two adjacent output clock signals of the plurality of output clock signals according to a prediction selection signal and that generates a fraction part frequency signal using the fraction part phase signal, the prediction selection signal being generated according to a fraction part phase signal indicating fraction part phase information and a signal indicating the current edge position information.