ADPLL Frequency Locking with FLL for Fast Stable Clock Acquisition
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Solution Overview
Problem
Conventional all-digital phase locked loops (ADPLLs) face issues with frequency locking behavior, leading to timing violations, false locks, and excessive frequency overshoots, especially when dealing with large frequency offsets or wide lock ranges, which can result in unstable output frequencies and incorrect clocking of digital signal processors.
Innovation Solution
The integration of a frequency locked loop (FLL) with an ADPLL, utilizing common components like a digitally controlled oscillator, time-to-digital converter, and feedback divider, allows for increased sensitivity to frequency changes and faster locking times, reducing frequency overshoots by using frequency control words and loop filters to adjust oscillator frequencies and phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the bandwidth of the ADPLL is enlarged to accelerate frequency locking, then the locking speed is improved, but the oscillator experiences large modulation over a wide frequency range causing frequency overshoots and timing violations
Solution Approach 1:
The patent segments the frequency locking process into two distinct stages: a frequency acquisition stage using FLL with large bandwidth for fast locking, and a phase tracking stage using PLL with narrow bandwidth for stable output. This segmentation allows each stage to operate with optimized parameters without compromising the other.
Solution Approach 2:
The system dynamically switches between FLL and PLL modes based on the locking progress. The controller monitors the frequency offset and transitions from FLL to PLL when the offset becomes small, adapting the loop characteristics to the current operating conditions to maintain both speed and stability.
2Adaptability or versatility
If the lock range of the ADPLL is widened to handle large frequency offsets, then the adaptability is improved, but false locks occur when phase words wrap causing unstable output frequency
Solution Approach 1:
The FLL acts as an intermediary stage that handles large frequency offsets before the PLL engages. By using frequency error detection instead of phase error detection, the FLL prevents phase word wrapping issues and guides the system through the large offset range without causing false locks.
Solution Approach 2:
The patent replaces the conventional phase-based detection mechanism with a frequency-based detection mechanism in the FLL stage. This substitution eliminates the phase wrapping problem that causes false locks when dealing with large frequency offsets.
3Measurement precision
If the ADPLL uses conventional phase locking from the start, then the phase accuracy is improved, but the frequency locking time becomes excessively long when frequency offset is large
Solution Approach 1:
The FLL performs preliminary frequency alignment before the PLL engages in precise phase tracking. This preliminary action brings the frequency offset to a small value, enabling the subsequent PLL operation to achieve high phase accuracy without requiring excessive locking time.
Solution Approach 2:
The patent maintains continuous frequency correction throughout the locking process by keeping the FLL operational in parallel with or transitioning to the PLL. This continuous action ensures both fast initial locking and sustained phase accuracy without interruption or excessive delay.
Data Source
AI summary
A hardware device includes a frequency lock loop (FLL) that includes a phase loop filter, and a phase lock loop (PLL) such as an all digital PLL (ADPLL) that includes a frequency loop filter. A controller provides a first control signal to the FLL and a second control signal to the PLL when the device operates the same. The device can also include a digital controlled oscillator (DCO) and part of one or more of the FLL and the PLL. The FLL and the PLL include first and second filters, respectively. The filters are coupled to the DCO. A time-to-digital converter (TDC) and a divider receive an input from the DCO. The controller forms a first loop with the first filter, the TDC, and the divider, and the controller forms a second loop with the second filter, the TDC, and the divider.