ADPLL Frequency Detector Freeze Control for Loop Stability
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Solution Overview
Problem
Existing all digital phase locked loop (ADPLL) designs face instability and inaccurate phase error propagation due to large perturbations, such as those caused by settling time in DCO varactor banks or spikes in power amplifiers, which can violate RF system specifications.
Innovation Solution
The implementation of a frequency detector that differentiates phase errors and integrates frequency errors, allowing the loop to be frozen during perturbations, preventing instability and oscillation, and resuming operation once the perturbation passes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a phase detector is used to generate phase error in the PLL, then phase comparison can be performed, but large perturbations cause inaccurate phase error propagation and loop instability
Solution Approach 1:
A perturbation detector is introduced as an intermediary component between the phase detector and loop filter. This mediator monitors the phase error signal for large perturbations and triggers a freeze condition when detected, preventing inaccurate phase error propagation while maintaining normal operation during standard conditions.
Solution Approach 2:
The system performs preliminary detection of perturbations before they can cause instability. By monitoring the phase error signal in advance and freezing the loop proactively when perturbations are detected, the system prevents subsequent inaccurate phase error propagation and maintains stability.
2Duration of action of stationary object
If the PLL operation continues during perturbations, then phase accumulation is maintained, but the loop may become unstable due to severe perturbations
Solution Approach 1:
The system dynamically adjusts its operation mode based on perturbation conditions. During normal operation, the loop runs continuously to maintain phase accumulation. When perturbations are detected, the system transitions to a frozen state, and automatically returns to continuous operation when perturbations subside, optimizing both stability and continuity.
Solution Approach 2:
The perturbation detector provides feedback about the phase error signal condition to the freeze control logic. This feedback mechanism enables the system to automatically detect when perturbations occur and trigger the appropriate freeze action, maintaining stability while preserving phase accumulation continuity when safe.
3Reliability
If the loop is frozen during perturbations, then instability and oscillation are prevented, but phase accumulation must be temporarily suspended
Solution Approach 1:
The system skips through perturbation periods by freezing the loop, allowing harmful signals to pass without affecting the accumulated phase. This temporary suspension is optimized to be as brief as possible, resuming operation immediately when perturbations subside, minimizing time loss while maintaining stability.
4Reliability
If a perturbation detection mechanism is added to the PLL, then loop stability during perturbations is improved, but device complexity increases
Solution Approach 1:
The patent replaces complex analog perturbation detection mechanisms with digital signal processing approaches. The perturbation detector uses digital comparison of phase error magnitudes against thresholds, and the freeze control uses digital state machine logic, substituting simpler digital circuits for potentially complex analog solutions.
Data Source
AI summary
A novel mechanism that is operative to observe and compare the differentiated phase of the reference and variable PLL loop signals using a frequency detector. The resultant phase differentiated error is then accumulated to yield the phase error. The operation of the loop with the frequency detector is mathematically equivalent to that of the phase detector. A frequency error accumulator is used to generate the integral of the frequency error. The frequency error accumulator also enables stopping the accumulation of the frequency upon detection of a sufficiently large perturbation, effectively freezing the operation of the loop as subsequent frequency error updates are not accumulated. Upon removal of the phase freeze event, accumulation of the frequency error and consequently normal loop operation resumes.