ADPLL Instant Lock Using Initial Phase Compensation
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Solution Overview
Problem
Low-bandwidth PLLs face a trade-off between bandwidth requirements and performance metrics, resulting in prolonged locking times and increased noise suppression, which negatively impacts data throughput and power consumption.
Innovation Solution
The implementation of an all-digital phase-locked loop (ADPLL) circuit with a 'one-shot' or instant lock mechanism, utilizing a time-to-digital converter (TDC), digital phase compensation, and a digitally controlled oscillator (DCO) to achieve near-zero settling time by setting initial conditions for building blocks within the loop, allowing for rapid phase and frequency lock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If low bandwidth is used in PLL, then noise suppression is improved, but locking time increases
Solution Approach 1:
The patent applies preliminary action by pre-setting the initial conditions of the VCO phase and frequency to match the incoming signal characteristics before actual signal arrival. This preliminary synchronization eliminates the traditional locking process, achieving instant lock without the trade-off between noise suppression and locking time. The system performs the synchronization action in advance, so when the signal arrives, phase alignment is already achieved.
2Loss of time
If high bandwidth is used in PLL, then locking time is reduced, but noise increases
Solution Approach 1:
By pre-synchronizing the VCO phase and frequency to match expected signal characteristics, the system achieves rapid locking without requiring high bandwidth. The preliminary action of setting initial conditions eliminates the need for aggressive bandwidth settings, thereby avoiding the noise penalty associated with high-bandwidth PLL designs.
3Reliability
If traditional PLL locking procedure is used, then phase and frequency lock is achieved, but data throughput decreases due to prolonged switching times
Solution Approach 1:
The system performs preliminary synchronization of phase and frequency before data transmission begins. This advance preparation eliminates the locking period that would otherwise occur at the start of each data package, enabling continuous data transmission without interruptions for phase locking, thereby maximizing data throughput while maintaining reliable synchronization.
4Reliability
If traditional PLL is used, then frequency synthesis is achieved, but power consumption increases due to prolonged locking periods
Solution Approach 1:
By pre-setting the VCO initial conditions to match the target frequency and phase, the system achieves frequency synthesis instantly without the prolonged locking period required by traditional PLLs. This eliminates the extended high-power state during locking, significantly reducing overall power consumption while maintaining reliable frequency synthesis.
Data Source
AI summary
Systems and methods reduce a locking time of a type-II all-digital phase-locked loop (ADPLL) circuit by performing steps that comprise receiving a reference signal having a reference frequency and setting a digitally controlled oscillator (DCO) to a target frequency greater than the reference frequency. The DCO generates an output signal that is used to generate a feedback signal. A time-to-digital converter is used to determine an initial phase difference between the reference signal and the feedback signal, and a digital initial phase compensation circuit adjusts the initial phase difference to a substantially zero phase difference to reduce the locking time of the ADPLL circuit such that the ADPLL circuit reaches a steady-state condition in ten or fewer cycles of the reference signal.